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公开(公告)号:US20220148953A1
公开(公告)日:2022-05-12
申请号:US17093090
申请日:2020-11-09
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
IPC: H01L23/498 , H01L25/18 , H01L23/31 , H01L21/56 , H01L21/48
Abstract: A reconstituted substrate, a packaged assembly comprising a reconstituted substrate, and methods for fabricating a reconstituted substrate. An example reconstituted substrate generally includes multiple package-level substrates implemented with different substrate technologies and held together. An example method for fabricating a reconstituted substrate generally includes forming multiple package-level substrates implemented with different substrate technologies, arranging the multiple package-level substrates, and adding a material to hold the multiple package-level substrates together.
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公开(公告)号:US20210343684A1
公开(公告)日:2021-11-04
申请号:US16864363
申请日:2020-05-01
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit package having a land-side capacitor electrically coupled to an embedded capacitor. One example integrated circuit package generally includes a package substrate having a first capacitor embedded therein, a semiconductor die disposed above the package substrate, and a second capacitor disposed below the package substrate and electrically coupled to the first capacitor.
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公开(公告)号:US20230246024A1
公开(公告)日:2023-08-03
申请号:US18298211
申请日:2023-04-10
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
CPC classification number: H01L27/0805 , H01L28/90 , H01L25/105 , H01L29/945 , H01L29/66181 , H01L28/40 , H10B12/37 , H10B12/038 , H10B12/39
Abstract: Certain aspects of the present disclosure provide a capacitor assembly, a stacked capacitor assembly, an integrated circuit (IC) assembly comprising such a stacked capacitor assembly, and methods for fabricating the same. One exemplary capacitor assembly generally includes a first array of trench capacitors and a second array of trench capacitors. The second array of trench capacitors may be disposed adjacent to and electrically coupled to the first array of trench capacitors. Additionally, the second array of trench capacitors may be inverted with respect to the first array of trench capacitors.
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公开(公告)号:US20220384328A1
公开(公告)日:2022-12-01
申请号:US17334610
申请日:2021-05-28
Applicant: QUALCOMM Incorporated
Inventor: Kuiwon KANG , Hong Bok WE , Chin-Kwan KIM , Milind SHAH
IPC: H01L23/498 , H01L23/00 , H01L21/48
Abstract: A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects comprising a plurality of protruding pad interconnects, and a solder resist layer located over the at least one dielectric layer, the solder resist layer comprising a thickness that is greater than a thickness of the plurality of protruding pad interconnects. A protruding pad interconnect may include a first pad portion and a second pad portion.
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公开(公告)号:US20210376493A1
公开(公告)日:2021-12-02
申请号:US16886086
申请日:2020-05-28
Applicant: QUALCOMM Incorporated
Inventor: Milind SHAH , Chin-Kwan KIM , Jaehyun YEON , Rajneesh KUMAR , Suhyung HWANG
Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate.
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公开(公告)号:US20230369234A1
公开(公告)日:2023-11-16
申请号:US17741986
申请日:2022-05-11
Applicant: QUALCOMM Incorporated
Inventor: Yangyang SUN , Srikanth KULKARNI , Lily ZHAO , Milind SHAH
IPC: H01L23/538 , H01L25/16 , H01L21/48 , H01L23/498 , H01L23/31
CPC classification number: H01L23/5386 , H01L25/165 , H01L21/486 , H01L23/49894 , H01L23/3121 , H01L23/3135 , H01L24/32
Abstract: A package comprising a substrate comprising a first surface and a second surface; a first integrated device coupled to the first surface of the substrate; an interconnection die coupled to the first surface of the substrate; a first encapsulation layer coupled to the first surface of the substrate, wherein the first encapsulation layer encapsulates the first integrated device and the interconnection die; and a second integrated device coupled to the second surface of the substrate.
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公开(公告)号:US20220131281A1
公开(公告)日:2022-04-28
申请号:US17568596
申请日:2022-01-04
Applicant: QUALCOMM Incorporated
Inventor: Milind SHAH , Chin-Kwan KIM , Jaehyun YEON , Rajneesh KUMAR , Suhyung HWANG
Abstract: An antenna-in-package (AiP) module is described. The AiP module includes an antenna sub-module. The antenna sub-module is composed of a first package substrate including an antenna side surface having a first group of antennas placed along a first portion of the antenna side surface and a second group of antennas placed along a second portion of the antenna side surface. The first package substrate is composed of a non-linear portion between the first group of antennas and the second group of antennas. The AiP module includes an active circuit sub-module placed on an active side surface of the first package substrate opposite the first group of antennas or the second group of antennas on the antenna side surface of the first package substrate. The active circuit includes a power management (PM) chip and a radio frequency (RF) chip coupled to a second package substrate coupled to the first package substrate.
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公开(公告)号:US20210257321A1
公开(公告)日:2021-08-19
申请号:US16789863
申请日:2020-02-13
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
IPC: H01L23/00
Abstract: Aspects of the present disclosure provide an integrated circuit package having an inductive element with a magnetic core. An example integrated circuit package generally includes a semiconductor die, a redistribution layer, and a magnetic core. The semiconductor die includes a metal layer having first conductive traces and conductive pillars coupled to and extending from the metal layer. The redistribution layer is disposed below the semiconductor die and includes second conductive traces. A portion of the first conductive traces, a portion of the conductive pillars, and a portion of the second conductive traces are arranged to form an inductive element disposed below a portion of the semiconductor die. The magnetic core is disposed in the inductive element.
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公开(公告)号:US20220108968A1
公开(公告)日:2022-04-07
申请号:US17061737
申请日:2020-10-02
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM , Abdolreza LANGARI
Abstract: Certain aspects of the present disclosure generally relate to an integrated circuit assembly. One example integrated circuit assembly generally includes a first reconstituted assembly, a second reconstituted assembly, and a third reconstituted assembly. The first reconstituted assembly comprises at least one passive component and a first bonding layer. The second reconstituted assembly is disposed above the first reconstituted assembly and comprises one or more first semiconductor dies, a second bonding layer bonded to the first bonding layer of the first reconstituted assembly, and a third bonding layer. The third reconstituted assembly is disposed above the second reconstituted assembly and comprises one or more second semiconductor dies and a fourth bonding layer bonded to the third bonding layer of the second reconstituted assembly.
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公开(公告)号:US20220013444A1
公开(公告)日:2022-01-13
申请号:US16927823
申请日:2020-07-13
Applicant: QUALCOMM Incorporated
Inventor: Jonghae KIM , Milind SHAH , Periannan CHIDAMBARAM
IPC: H01L23/498 , H03F3/213
Abstract: A package that includes a power amplifier and a substrate coupled to the power amplifier. The substrate includes an encapsulation layer, a capacitor device located in the encapsulation layer, an inductor located in the encapsulation layer, at least one first dielectric layer coupled to a first surface of the encapsulation layer, and a plurality of first interconnects coupled to the first surface of the encapsulation layer. The plurality of first interconnects is located at least in the at least one first dielectric layer. The plurality of first interconnects is coupled to the capacitor device and the inductor. The inductor and the capacitor device are configured to be electrically coupled together to operate as elements of a matching network for the power amplifier. The capacitor device is configured to be coupled to ground.
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