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    PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS
    1.
    发明申请
    PACKAGE COMPRISING A SUBSTRATE WITH HIGH-DENSITY INTERCONNECTS 有权

    公开(公告)号：US20230073823A1

    公开(公告)日：2023-03-09

    申请号：US17471061

    申请日：2021-09-09

    申请人： QUALCOMM Incorporated

    发明人： Chin-Kwan KIM ,  Kuiwon KANG ,  Joan Rey Villarba BUOT

    IPC分类号： H01L23/522 ,  H01L25/065 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00

    摘要： A package comprising a substrate and an integrated device coupled to the substrate. The substrate includes a core layer comprising a first surface and a second surface; at least one first dielectric layer coupled to the first surface of the core layer; at least one second dielectric layer coupled to the second surface of the core layer; at least one core interconnect that extends through the core layer and at least one dielectric layer from the at least first dielectric layer and/or the at least one second dielectric layer; a plurality of high-density interconnects comprising a first minimum width and a first minimum spacing; and a plurality of interconnects comprising a second minimum width and a second minimum spacing. The second minimum width is greater than the first minimum width. The second minimum spacing is greater than the first minimum spacing.

    INTEGRATED DEVICE COMPRISING EMBEDDED PACKAGE ON PACKAGE (PoP) DEVICE
    2.
    发明申请
    INTEGRATED DEVICE COMPRISING EMBEDDED PACKAGE ON PACKAGE (PoP) DEVICE 审中-公开

    公开(公告)号：US20190081027A1

    公开(公告)日：2019-03-14

    申请号：US16185635

    申请日：2018-11-09

    申请人： QUALCOMM Incorporated

    发明人： Rajneesh KUMAR ,  Chin-Kwan KIM ,  Milind SHAH

    IPC分类号： H01L25/10 ,  H01L23/66 ,  H01L23/552 ,  H01L25/065 ,  H04W4/80 ,  H04W4/00 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L25/16

    摘要： A device that includes a printed circuit board (PCB), a package on package (PoP) device, a first encapsulation layer, and a second encapsulation layer. The package on package (PoP) device is coupled to the printed circuit board (PCB). The package on package (PoP) device includes a first package having a first electronic package component, a second package coupled to the first package, a gap controller configured to provide a spacing between the first electronic package component and the second package. The gap controller includes a spacer and an adhesive layer. The first encapsulation layer is formed between the first package and the second package. The first encapsulation layer is configured to at least partially encapsulate the gap controller including the spacer and the adhesive layer. The second encapsulation layer is configured to at least partially encapsulates the package on package (PoP) device. The device is configured to provide cellular functionality.

    SUBSTRATE AND METHOD OF FORMING THE SAME
    8.
    发明申请
    SUBSTRATE AND METHOD OF FORMING THE SAME 有权
    基板及其形成方法

    公开(公告)号：US20150333004A1

    公开(公告)日：2015-11-19

    申请号：US14276763

    申请日：2014-05-13

    申请人： QUALCOMM Incorporated

    发明人： Houssam Wafic JOMAA ,  Omar James BCHIR ,  Kuiwon KANG ,  Chin-Kwan KIM

    IPC分类号： H01L23/522 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5383 ,  H01L23/5384 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods and apparatus for formation of a semiconductor substrate with photoactive dielectric material, embedded traces, a padless skip via extending through two dielectric layers, and a coreless package are provided. In one embodiment, a method for forming a core having a copper layer; laminating the copper layer a photoactive dielectric layer; forming a plurality of trace patterns in the photoactive dielectric layer; plating the plurality of trace patterns to form a plurality of traces; forming an insulating dielectric layer on the photoactive dielectric layer; forming a via through the insulating dielectric layer and the photoactive dielectric layer; forming additional routing patterns on the insulating dielectric layer; removing the core; and applying a solder mask.

    摘要翻译： 提供了用光电介质材料形成半导体衬底的方法和装置，嵌入迹线，延伸穿过两个电介质层的无衬垫跳过和无芯封装。 在一个实施例中，一种形成具有铜层的芯的方法; 将铜层层压成光电介质层; 在光电介质层中形成多个迹线图案; 电镀所述多个迹线图案以形成多个迹线; 在光电介质层上形成绝缘介电层; 通过绝缘介电层和光电介质层形成通孔; 在所述绝缘介电层上形成额外的布线图案; 去除核心; 并施加焊接掩模。

    UNIFORM VIA PAD STRUCTURE
    9.
    发明申请
    UNIFORM VIA PAD STRUCTURE 审中-公开

    公开(公告)号：US20200219803A1

    公开(公告)日：2020-07-09

    申请号：US16724247

    申请日：2019-12-21

    申请人： QUALCOMM Incorporated

    发明人： Kuiwon KANG ,  Chin-Kwan KIM ,  Aniket PATIL ,  Jaehyun YEON

    IPC分类号： H01L23/498 ,  H01L21/48

    摘要： Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

    ASYMMETRIC ANTENNA STRUCTURE
    10.
    发明申请
    ASYMMETRIC ANTENNA STRUCTURE 审中-公开

    公开(公告)号：US20200212545A1

    公开(公告)日：2020-07-02

    申请号：US16236726

    申请日：2018-12-31

    申请人： QUALCOMM Incorporated

    发明人： Hong Bok WE ,  Chin-Kwan KIM ,  Jaehyun YEON ,  Suhyung HWANG

    IPC分类号： H01Q1/24 ,  H01Q1/08 ,  H01Q9/12

    摘要： Certain aspects of the present disclosure provide an asymmetric antenna structure. An example antenna device generally includes a first antenna element, a second antenna element, and a flexible coupling element asymmetrically positioned between surfaces of the first and second antenna elements and electrically coupling the first antenna element to the second antenna element.