公开(公告)号：US20080094878A1

公开(公告)日：2008-04-24

申请号：US11963794

申请日：2007-12-22

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Yuen Chan ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Yuen Chan ,  Anirudh Devgan

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。 环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US07515491B2

公开(公告)日：2009-04-07

申请号：US11685905

申请日：2007-03-14

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.

摘要翻译： 用于评估对静态存储器单元访问时间的泄漏影响的方法提供了一种用于提高存储器阵列的性能超过现有水平/产量的机制。 通过改变与被测试的静态存储器单元连接到同一位线的其它静态存储单元的状态，可以观察到泄漏对单元访问时间的影响。 可以进一步观察泄漏效应，同时改变存储器单元的内部对称性，操作电池并观察不对称操作引起的性能变化。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。

公开(公告)号：US07483322B2

公开(公告)日：2009-01-27

申请号：US11963794

申请日：2007-12-22

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储单元性能的环形振荡器行电路在实际的存储器电路环境中提供电路延迟和性能测量。 环形振荡器用一行存储器单元实现，并且具有连接到一个或多个位线以及与环形振荡器单元基本相同的其它存储器单元的输出。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US07301835B2

公开(公告)日：2007-11-27

申请号：US11225652

申请日：2005-09-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

公开(公告)号：US20070058466A1

公开(公告)日：2007-03-15

申请号：US11225652

申请日：2005-09-13

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

摘要翻译： 用于评估静态存储单元动态稳定性的内部非对称方法和电路为提高存储器阵列的性能提供了超越现有水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

公开(公告)号：US07376001B2

公开(公告)日：2008-05-20

申请号：US11250019

申请日：2005-10-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Yuen H. Chan ,  Anirudh Devgan

IPC分类号： G11C11/00

CPC分类号： G11C29/50 ,  G11C29/50012

摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 通过该方法操作在一行存储器单元中实现的具有连接到一个或多个位线的输出的环形振荡器以及与环形振荡器单元基本相同的其它存储器单元。 可以包括用于提供完全功能的存储器阵列的逻辑，使得当环形振荡器行字线被禁用时，除了环形振荡器单元之外的单元可以用于存储。 形成环形振荡器电路中使用的静态存储单元的各个交叉耦合的逆变器级的一个或两个电源轨可以彼此隔离，以引入电压不对称，从而可以评估电路不对称对延迟的影响。

公开(公告)号：US20070291562A1

公开(公告)日：2007-12-20

申请号：US11838341

申请日：2007-08-14

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

摘要翻译： 用于评估静态存储单元动态稳定性的内部非对称方法和电路为提高存储器阵列的性能提供了超越现有水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储单元的内部对称性，操作单元并观察不对称操作引起的性能变化，可以通过设计和操作环境研究SRAM单元的动态稳定性。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 可以在生产或测试晶片中制造具有至少一个测试单元的存储器阵列，并且可以探测存储器单元的内部节点以提供进一步的信息。

公开(公告)号：US07304895B2

公开(公告)日：2007-12-04

申请号：US11225571

申请日：2005-09-13

申请人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv V. Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C29/006 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5002

摘要： Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

摘要翻译： 用于评估静态存储单元动态稳定性的位线可变方法和电路为提高存储器阵列的性能提供了超出当前水平/产量的机制。 通过改变静态随机存取存储器（SRAM）存储器单元的位线预充电电压，操作单元并观察由位线电压变化引起的性能变化，可以研究SRAM单元的动态稳定性，并通过设计和 操作环境。 或者或组合地，可以改变单元的输出处的负载以影响电池的性能。 此外，电池电源电压可以分开并设置为不同的电平，以研究电池不对称与位线预充电电压差的结合。

公开(公告)号：US20070153599A1

公开(公告)日：2007-07-05

申请号：US11685905

申请日：2007-03-14

申请人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

发明人： Rajiv Joshi ,  Qiuyi Ye ,  Anirudh Devgan

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/006 ,  G11C29/12005 ,  G11C29/24 ,  G11C2029/5002

摘要： A method for evaluating leakage effects on static memory cell access time provides a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the states of other static memory cells connected to the same bitline as a static memory cell under test, the effect of leakage on the access time of the cell can be observed. The leakage effects can further be observed while varying the internal symmetry of the memory cell, operating the cell and observing changes in performance caused by the asymmetric operation. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage.

摘要翻译： 用于评估对静态存储器单元访问时间的泄漏影响的方法提供了一种用于提高存储器阵列的性能超过现有水平/产量的机制。 通过改变与被测试的静态存储器单元连接到同一位线的其它静态存储单元的状态，可以观察到泄漏对单元访问时间的影响。 可以进一步观察泄漏效应，同时改变存储器单元的内部对称性，操作电池并观察不对称操作引起的性能变化。 可以通过将一个或两个电源轨输入分成单元并且向每个交叉耦合级提供不同的电源电压或电流来引入不对称性。

公开(公告)号：US5406509A

公开(公告)日：1995-04-11

申请号：US46249

申请日：1993-04-12

申请人： Stanford R. Ovshinsky ,  Qiuyi Ye ,  David A. Strand ,  Wolodymyr Czubatyj

发明人： Stanford R. Ovshinsky ,  Qiuyi Ye ,  David A. Strand ,  Wolodymyr Czubatyj

IPC分类号： G11C11/56 ,  G11C16/02 ,  H01L27/24 ,  H01L45/00 ,  G11C17/14

CPC分类号： G11C13/0004 ,  G11C11/56 ,  G11C11/5678 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/144 ,  G11C13/04 ,  G11C2213/72

摘要： The present invention comprises an electrically operated, directly overwritable, multibit, single-cell memory element. The memory element includes a volume of memory material which defines the single cell memory element. The memory material is characterized by: (1) a large dynamic range of electrical resistance values; and (2) the ability to be set at one of a plurality of resistance values within said dynamic range in response to selected electrical input signals so as to provide said single cell with multibit storage capabilities. The memory element also includes a pair of spacedly disposed contacts for supplying the electrical input signal to set the memory material to a selected resistance value within the dynamic range. At least a filamentary portion of the single cell memory element being setable, by the selected electrical signal to any resistance value in said dynamic range, regardless of the previous resistance value of said material. The memory element further includes a filamentary portion controlling means disposed between the volume of memory material and at least one of the spacedly disposed contacts. The controlling means defining the size and position of the filamentary portion during electrical formation of the memory element and limiting the size and confining the location of the filamentary portion during use of the memory element, thereby providing for a high current density within the filamentary portion of the single cell memory element upon input of a very low total current electrical signal to the spacedly disposed contacts.

摘要翻译： 本发明包括电操作的直接覆盖的多位单个单元存储元件。 存储元件包括限定单个单元存储元件的一定量的存储器材料。 记忆材料的特征在于：（1）电阻值的大动态范围; 以及（2）响应于所选择的电输入信号在所述动态范围内被设置为多个电阻值之一的能力，以便向所述单个单元提供多位存储能力。 存储元件还包括一对间隔设置的触点，用于提供电输入信号以将存储器材料设置在动态范围内的所选电阻值。 所述单个单元存储元件的至少一个细长部分可被所选择的电信号设定到所述动态范围内的任何电阻值，而与所述材料的先前电阻值无关。 存储元件还包括设置在存储器材料体积与间隔设置的触点中的至少一个之间的丝状部分控制装置。 控制装置在存储元件的电气形成期间限定丝状部分的尺寸和位置，并且在存储元件的使用期间限制尺寸并限制丝状部分的位置，由此提供丝网部分内的高电流密度 当输入非常低的总电流电信号到间隔布置的触点时，单个单元存储元件。