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Patent Agency Ranking
公开(公告)号：US20200209911A1
公开(公告)日：2020-07-02
申请号：US16707957
申请日：2019-12-09
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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公开(公告)号：US09298228B1
公开(公告)日：2016-03-29
申请号：US14810410
申请日：2015-07-27
Applicant: Rambus Inc.
Inventor： Abhijit M. Abhyankar , Ravindranath Kollipara , Thomas J. Giovannini , Ming Li , David A. Secker , Arun Vaidyanath , Donald R. Mullen , Adrian F. Torres
CPC classification number: G06F1/185
Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.
Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。
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公开(公告)号：US20220300030A1
公开(公告)日：2022-09-22
申请号：US17715869
申请日：2022-04-07
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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公开(公告)号：US11327524B2
公开(公告)日：2022-05-10
申请号：US16707957
申请日：2019-12-09
Applicant: Rambus Inc.
Inventor： Scott C. Best , Abhijit M. Abhyankar , Kun-Yung Chang , Frank Lambrecht
Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.
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公开(公告)号：US10678459B2
公开(公告)日：2020-06-09
申请号：US15745396
申请日：2016-07-14
Applicant: Rambus Inc.
Inventor： Suresh Rajan , Abhijit M. Abhyankar , Ravindranath Kollipara , David A. Secker
Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
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