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    MULTI-DIE MEMORY DEVICE
    2.
    发明申请
    MULTI-DIE MEMORY DEVICE 有权

    公开(公告)号：US20210193215A1

    公开(公告)日：2021-06-24

    申请号：US17135112

    申请日：2020-12-28

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C11/4093 ,  G11C11/4096 ,  G11C5/02 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Multi-die memory device
    3.
    发明授权
    Multi-die memory device 有权

    公开(公告)号：US10885971B2

    公开(公告)日：2021-01-05

    申请号：US16823122

    申请日：2020-03-18

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/04 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/48 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/00

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    Memory capacity expansion using a memory riser
    5.
    发明授权
    Memory capacity expansion using a memory riser 有权
    使用内存提升板的内存容量扩展

    公开(公告)号：US09298228B1

    公开(公告)日：2016-03-29

    申请号：US14810410

    申请日：2015-07-27

    Applicant: Rambus Inc.

    Inventor： Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  Thomas J. Giovannini ,  Ming Li ,  David A. Secker ,  Arun Vaidyanath ,  Donald R. Mullen ,  Adrian F. Torres

    IPC: H05K1/11 ,  H05K1/14 ,  G06F1/18

    CPC classification number: G06F1/185

    Abstract: A computing system having a memory riser sub-system. The computing system includes a motherboard with a memory module connector and a riser card inserted into the first memory module connector. A first mezzanine card is connected to the riser card. The first mezzanine card includes a first mezzanine memory module connector for a first memory module and a second mezzanine memory module connector for a second memory module. A memory channel electrically connects the memory controller to the first mezzanine memory module connector and the second mezzanine module connector via the motherboard, the first riser card and the first mezzanine card. The memory channel may be divided into a first data sub-channel connected to the first mezzanine memory module connector and a second data sub-channel connected to the second mezzanine memory module connector.

    Abstract translation: 具有存储器提升子子系统的计算系统。 计算系统包括具有存储器模块连接器的主板和插入到第一存储器模块连接器中的转接卡。 第一个夹层卡连接到转接卡。 第一夹层卡包括用于第一存储器模块的第一夹层存储器模块连接器和用于第二存储器模块的第二夹层存储器模块连接器。 存储通道经由主板，第一转接卡和第一夹层卡将存储器控制器电连接到第一夹层存储器模块连接器和第二夹层模块连接器。 存储器通道可以被分成连接到第一夹层存储器模块连接器的第一数据子通道和连接到第二夹层存储器模块连接器的第二数据子通道。

    MULTI-DIE MEMORY DEVICE
    7.
    发明申请
    MULTI-DIE MEMORY DEVICE 有权

    公开(公告)号：US20240404580A1

    公开(公告)日：2024-12-05

    申请号：US18657631

    申请日：2024-05-07

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C11/4093 ,  G11C5/02 ,  G11C5/04 ,  G11C11/406 ,  G11C11/4096 ,  H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

    MULTI-DIE MEMORY DEVICE
    9.
    发明申请
    MULTI-DIE MEMORY DEVICE 有权

    公开(公告)号：US20220139446A1

    公开(公告)日：2022-05-05

    申请号：US17540950

    申请日：2021-12-02

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  Ming Li

    IPC: G11C11/4093 ,  H01L25/10 ,  G11C5/02 ,  H01L25/18 ,  H01L25/065 ,  G11C11/4096 ,  G11C5/04 ,  H01L23/48 ,  G11C11/406 ,  H01L23/00

    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

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