公开(公告)号：US20140068169A1

公开(公告)日：2014-03-06

申请号：US13923184

申请日：2013-06-20

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Craig E. Hampel ,  Ian Shaeffer ,  Scott C. Best

IPC: G11C7/10

CPC classification number: G11C7/1072 ,  G06F13/1684 ,  G06F13/4234 ,  G11C5/00

Abstract: A memory module includes a substrate having signal lines thereon that form a control path and a plurality of data paths. A plurality of memory devices are mounted on the substrate. Each memory device is coupled to the control path and to a distinct data path. The memory module includes control circuitry to enable each memory device to process a distinct respective memory access command in a succession of memory access commands and to output data on the distinct data path in response to the processed memory access command.

Abstract translation: 存储器模块包括其上具有信号线的衬底，其形成控制路径和多个数据路径。 多个存储器件安装在基片上。 每个存储器件耦合到控制路径和不同的数据路径。 存储器模块包括控制电路，以使得每个存储器设备能够在一系列存储器访问命令中处理不同的相应存储器访问命令，并且响应于处理的存储器访问命令在不同的数据路径上输出数据。

公开(公告)号：US11533077B2

公开(公告)日：2022-12-20

申请号：US17023169

申请日：2020-09-16

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Carl Werner

IPC: H04B3/32

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.

公开(公告)号：US20220165326A1

公开(公告)日：2022-05-26

申请号：US17439215

申请日：2020-03-16

Applicant: RAMBUS INC.

Inventor： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C8/18 ,  G06F12/0895

Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US10812138B2

公开(公告)日：2020-10-20

申请号：US16544475

申请日：2019-08-19

Applicant: Rambus Inc.

Inventor： Frederick Ware ,  Carl Werner

IPC: H04B3/32

Abstract: Disclosed is a signaling circuit. A switch circuit generates an internal reference supply voltage and an internal lower supply voltage, from first and second power supply voltages. A transmit circuit drives a high bit from the first power supply voltage, and drives a low bit from the internal lower supply voltage. The second terminal of the data output is connected to the internal reference supply voltage.