公开(公告)号：US20240354014A1

公开(公告)日：2024-10-24

申请号：US18655510

申请日：2024-05-06

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Steven C. Woo ,  Michael Raymond Miller

IPC: G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/061 ,  G06F3/0673

Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.

公开(公告)号：US20240295961A1

公开(公告)日：2024-09-05

申请号：US18598323

申请日：2024-03-07

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Steven C. Woo ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40611 ,  G11C11/40615

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

公开(公告)号：US20240257860A1

公开(公告)日：2024-08-01

申请号：US18566558

申请日：2022-05-31

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Brent Steven Haukness ,  Gary Bela Bronner

IPC: G11C11/4074 ,  G06F12/02 ,  G11C11/408 ,  G11C11/4091

CPC classification number: G11C11/4074 ,  G06F12/0223 ,  G11C11/4085 ,  G11C11/4091

Abstract: A dynamic random access memory (DRAM) device includes memory core circuitry and power supply circuitry. The memory core circuitry includes an array of DRAM storage cells, with ones of the DRAM storage cells coupled to wordline and bitline power supply busses. The power supply circuitry is coupled to the wordline and bitline power supply busses. The power supply circuitry is responsive to a control signal to generate one of a first set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a first normal mode of operation, or to generate a second set of respective wordline and bitline voltages for application to the wordline and bitline power supply busses in a second normal mode of operation. A value of the control signal is based on a temperature parameter associated with the DRAM device.

公开(公告)号：US12020740B2

公开(公告)日：2024-06-25

申请号：US16973241

申请日：2019-05-25

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G11C11/406

CPC classification number: G11C11/40615 ,  G11C11/40611 ,  G11C11/40626

Abstract: An integrated circuit memory device includes an array of storage cells configured into multiple banks. Each bank includes multiple segments. Register storage stores per-segment values representing per-segment refresh parameters. Refresh logic refreshes each segment in accordance with the corresponding per-segment value.

公开(公告)号：US20240118837A1

公开(公告)日：2024-04-11

申请号：US18487955

申请日：2023-10-16

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F11/10 ,  G11C7/10 ,  G11C29/02

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0638 ,  G06F3/0673 ,  G06F11/1076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1087 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/023 ,  G11C29/028 ,  G11C2029/0411 ,  G11C2207/107

Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.

公开(公告)号：US11934654B2

公开(公告)日：2024-03-19

申请号：US17544584

申请日：2021-12-07

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Steven C. Woo ,  Thomas Vogelsang

IPC: G06F3/06 ,  G11C11/406

CPC classification number: G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40611 ,  G11C11/40615

Abstract: An integrated circuit (IC) memory device includes an array of storage cells configured into multiple banks. Interface circuitry receives refresh commands from a host memory controller to refresh the multiple banks for a first refresh mode. On-die refresh control circuitry selectively generates local refresh commands to refresh the multiple banks in cooperation with the host memory controller during a designated hidden refresh interval in a second refresh mode. Mode register circuitry stores a value indicating whether the on-die refresh control circuitry is enabled for use during the second refresh mode. The interface circuitry includes backchannel control circuitry to transmit a corrective action control signal during operation in the second refresh mode.

公开(公告)号：US11868619B2

公开(公告)日：2024-01-09

申请号：US17785269

申请日：2020-12-03

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Thomas Vogelsang ,  John Eric Linstadt

IPC: G06F3/06 ,  G11C11/406 ,  G06F13/16

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G11C11/40622 ,  G06F13/1636

Abstract: A memory controller combines information about which memory component segments are not being refreshed with the information about which rows are going to be refreshed next, to determine, for the current refresh command, the total number of rows that are going to be refreshed. Based on this total number of rows, the memory controller selects how long to wait after the refresh command before issuing a next subsequent command. When the combination of masked segments and the refresh scheme results in less than the ‘nominal’ number of rows typically refreshed in response to a single refresh command, the waiting period before the next command (e.g., non-refresh command) is issued may be reduced from the ‘nominal’ minimum time period, thereby allowing the next command to be issued earlier.

公开(公告)号：US20230377668A1

公开(公告)日：2023-11-23

申请号：US18138661

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C29/44 ,  G11C5/04

CPC classification number: G11C29/24 ,  G06F11/1008 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061 ,  G11C5/04

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US11775213B2

公开(公告)日：2023-10-03

申请号：US17323024

申请日：2021-05-18

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/061 ,  G06F3/0673

Abstract: A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

公开(公告)号：US11645212B2

公开(公告)日：2023-05-09

申请号：US17504739

申请日：2021-10-19

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Thomas Vogelsang ,  Joseph James Tringali ,  Pooneh Safayenikoo

IPC: G06F9/30 ,  G06F13/16 ,  H01L25/18 ,  H01L25/065

CPC classification number: G06F13/1668 ,  H01L25/0657 ,  H01L25/18 ,  H01L2225/06541

Abstract: Processing elements include interfaces that allow direct access to memory banks on one or more DRAMs in an integrated circuit stack. These additional (e.g., per processing element) direct interfaces may allow the processing elements to have direct access to the data in the DRAM stack. Based on the size/type of operands being processed, and the memory bandwidth of the direct interfaces, rate calculation circuitry on the processor die determines the speed each processing element and/or processing nodes within each processing element are operated.