公开(公告)号：US12086441B2

公开(公告)日：2024-09-10

申请号：US17461105

申请日：2021-08-30

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Steven C. Woo ,  Thomas Vogelsang

IPC: G06F3/06 ,  G06F1/08

CPC classification number: G06F3/064 ,  G06F1/08 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0688

Abstract: An interconnected stack of one or more Dynamic Random Access Memory (DRAM) die also has one or more custom logic, controller, or processor die. The custom die(s) of the stack include direct channel interfaces that allow direct access to memory regions on one or more DRAMs in the stack. The direct channels are time-division multiplexed such that each DRAM die is associated with a time slot on a direct channel. The custom die configures a first DRAM die to read a block of data and transmit it via the direct channel using a time slot that is assigned to a second DRAM die. The custom die also configures the second memory device to receive the first block of data in its assigned time slot and write the block of data.

公开(公告)号：US20240153548A1

公开(公告)日：2024-05-09

申请号：US18503022

申请日：2023-11-06

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G06F12/0895 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4087 ,  G11C2207/2245

Abstract: Disclosed is a memory system including a memory component having at least one tag row and at least one data row and multiple ways to hold a data group as a cache-line or cache-block. The memory system includes a memory controller that is connectable to the memory component to implement a cache and operable with the memory controller and the memory component in each of a plurality of operating modes including a first and second operating mode having differing addressing and timing requirements for accessing the data group. The first operating mode having placement of each of at least two ways of a data group in differing rows in the memory component, with tag access and data access not overlapped. The second operating mode having placement of all ways of a data group in a same row in the memory component, with tag access and data access overlapped.

公开(公告)号：US20220398198A1

公开(公告)日：2022-12-15

申请号：US17853735

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US11409659B2

公开(公告)日：2022-08-09

申请号：US17221639

申请日：2021-04-02

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20250021484A1

公开(公告)日：2025-01-16

申请号：US18782890

申请日：2024-07-24

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.

公开(公告)号：US12093180B2

公开(公告)日：2024-09-17

申请号：US17853735

申请日：2022-06-29

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

CPC classification number: G06F12/0868 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20220165326A1

公开(公告)日：2022-05-26

申请号：US17439215

申请日：2020-03-16

Applicant: RAMBUS INC.

Inventor： Frederick Ware ,  Thomas Vogelsang ,  Michael Raymond Miller ,  Collins Williams

IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C8/18 ,  G06F12/0895

Abstract: Disclosed is a memory system that has a memory controller and may have a memory component. The memory component may be a dynamic random access memory (DRAM). The memory controller is connectable to the memory component. The memory component has at least one data row and at least one tag row different from and associated with the at least one data row. The memory system is to implement a cache having multiple ways to hold a data group. The memory controller is operable in each of a plurality of operating modes. The operating modes include a first operating mode and a second operating mode. The first operating mode and the second operating mode have differing addressing and timing for accessing the data group. The memory controller has cache read logic that sends a cache read command, cache results logic that receives a response from the memory component, and cache fetch logic.

公开(公告)号：US20220076714A1

公开(公告)日：2022-03-10

申请号：US17410786

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Michael Raymond Miller

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/20 ,  G11C5/06

Abstract: A stacked processor-plus-memory device includes a processing die with an array of processing elements of an artificial neural network. Each processing element multiplies a first operand—e.g. a weight—by a second operand to produce a partial result to a subsequent processing element. To prepare for these computations, a sequencer loads the weights into the processing elements as a sequence of operands that step through the processing elements, each operand stored in the corresponding processing element. The operands can be sequenced directly from memory to the processing elements or can be stored first in cache. The processing elements include streaming logic that disregards interruptions in the stream of operands.

公开(公告)号：US20210326265A1

公开(公告)日：2021-10-21

申请号：US17221639

申请日：2021-04-02

Applicant: Rambus Inc.

Inventor： Michael Raymond Miller ,  Dennis Doidge ,  Collins Williams

IPC: G06F12/0868 ,  G06F3/06

Abstract: A device includes a memory controller and a cache memory coupled to the memory controller. The cache memory has a first set of cache lines associated with a first memory block and comprising a first plurality of cache storage locations, as well as a second set of cache lines associated with a second memory block and comprising a second plurality of cache storage locations. A first location of the second plurality of cache storage locations comprises cache tag data for both the first set of cache lines and the second set of cache lines.

公开(公告)号：US20210200680A1

公开(公告)日：2021-07-01

申请号：US17058492

申请日：2019-05-31

Applicant: RAMBUS INC.

Inventor： Thomas Vogelsang ,  Frederick A. Ware ,  Michael Raymond Miller ,  Collins Williams

IPC: G06F12/0864

Abstract: Disclosed is a dynamic random access memory that has columns, data rows, tag rows and comparators. Each comparator compares address bits and tag information bits from the tag rows to determine a cache hit and generate address bits to access data information in the DRAM as a multiway set associative cache.