公开(公告)号：US12026548B2

公开(公告)日：2024-07-02

申请号：US18493703

申请日：2023-10-24

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinseok Kim ,  Chang-Hyo Yu

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A task manager, a neural processing device, and a method for checking task dependencies thereof are provided. The task manager includes a task buffer configured to receive first and second tasks of different first and second types, a first queue configured to receive a first task descriptor for the first task from the task buffer, a second queue configured to receive a second task descriptor for the second task from the task buffer, a dependency checker configured to check dependencies of the first and second task descriptors, a third queue configured to receive the first task descriptor from the dependency checker, and a fourth queue configured to receive the second task descriptor from the dependency checker.

公开(公告)号：US20240211410A1

公开(公告)日：2024-06-27

申请号：US18500781

申请日：2023-11-02

Applicant: Rebellions Inc.

Inventor： Chang-Hyo Yu

IPC: G06F12/1027 ,  G06N3/04 ,  G06N3/08

CPC classification number: G06F12/1027 ,  G06N3/04 ,  G06N3/08

Abstract: A neural processing device and a method of updating translation lookaside buffer thereof are provided. The neural processing device includes at least one processor module each of which includes at least one micro translation lookaside buffer (TLB), a hierarchical memory that is accessed by the at least one micro TLB, and a command processor configured to update the at least one micro TLB in a push mode by generating a first update signal which indicates update of the at least one micro TLB and transmitting the first update signal to the at least one micro TLB.

公开(公告)号：US12008132B1

公开(公告)日：2024-06-11

申请号：US18338264

申请日：2023-06-20

Applicant: REBELLIONS INC.

Inventor： Myunghoon Choi ,  Chang-Hyo Yu

IPC: H04L29/06 ,  G06F21/62

CPC classification number: G06F21/6227

Abstract: A method for confidential computing is provided, which is performed by a security core including one or more processor, and includes storing first encrypted data associated with a first tenant in a first memory, in which the first encrypted data is obtained by performing encryption of the first plaintext data using a first encryption key associated with the first tenant, in response to receiving a request to access the first plaintext data, decrypting the first encrypted data using the first encryption key so as to generate the first plaintext data, and providing the first plaintext data to a main core that processes data stored in the first memory.

公开(公告)号：US20240152392A1

公开(公告)日：2024-05-09

申请号：US18493703

申请日：2023-10-24

Applicant: Rebellions Inc.

Inventor： Wongyu Shin ,  Miock Chi ,  Hongyun Kim ,  Jinseok Kim ,  Chang-Hyo Yu

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A task manager, a neural processing device, and a method for checking task dependencies thereof are provided. The task manager includes a task buffer configured to receive first and second tasks of different first and second types, a first queue configured to receive a first task descriptor for the first task from the task buffer, a second queue configured to receive a second task descriptor for the second task from the task buffer, a dependency checker configured to check dependencies of the first and second task descriptors, a third queue configured to receive the first task descriptor from the dependency checker, and a fourth queue configured to receive the second task descriptor from the dependency checker.

公开(公告)号：US11657261B1

公开(公告)日：2023-05-23

申请号：US17661414

申请日：2022-04-29

Applicant: Rebellions Inc.

Inventor： Jinwook Oh ,  Jinseok Kim ,  Kyeongryeol Bong ,  Wongyu Shin ,  Chang-Hyo Yu

IPC: G06N3/063 ,  G06F9/38 ,  G06F9/52 ,  G06F5/06

CPC classification number: G06N3/063 ,  G06F5/065 ,  G06F9/3877 ,  G06F9/52

Abstract: A neural processing device is provided. The neural processing device comprises a plurality of neural processors, a shared memory shared by the plurality of neural processors, a plurality of semaphore memories, and global interconnection. The plurality of neural processors generates a plurality of L3 sync targets, respectively. Each semaphore memory is associated with a respective one of the plurality of neural processors, and the plurality of semaphore memories receive and store the plurality of L3 sync targets, respectively. Synchronization of the plurality of neural processors is performed according to the plurality of L3 sync targets. The global interconnection connects the plurality of neural processors with the shared memory, and comprises an L3 sync channel through which an L3 synchronization signal corresponding to at least one L3 sync target is transmitted.