公开(公告)号：US20170084625A1

公开(公告)日：2017-03-23

申请号：US15265473

申请日：2016-09-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke TAKEUCHI ,  Eiji TSUKUDA ,  Kenichiro SONODA ,  Shibun TSUDA

IPC: H01L27/115 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US20140213030A1

公开(公告)日：2014-07-31

申请号：US14155961

申请日：2014-01-15

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。