公开(公告)号：US20230090409A1

公开(公告)日：2023-03-23

申请号：US17480007

申请日：2021-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji TSUKUDA ,  Katsumi EIKYU

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor substrate, a first dielectric film, a conductive film, at least one ferroelectric film, a second dielectric film, a memory gate electrode, a third dielectric film and a control gate electrode. The semiconductor substrate includes a source region and a drain region. The semiconductor substrate includes a first region and a second region between the source region and the drain region. The first dielectric film is formed on the first region. The conductive film is formed on the first dielectric film. The at least one ferroelectric film is formed on one hart of the conductive film. The second dielectric film is formed on the other part of the conductive film. The memory gate electrode is formed on the ferroelectric film. The third dielectric film is formed on the second region. The control gate electrode is formed on the third dielectric film.

公开(公告)号：US20180294033A1

公开(公告)日：2018-10-11

申请号：US16009535

申请日：2018-06-15

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro SONODA ,  Eiji TSUKUDA ,  Keiichi MAEKAWA

IPC: G11C16/10 ,  H01L29/792 ,  H01L29/06 ,  H01L27/12 ,  H01L27/11573 ,  H01L27/11568 ,  H01L21/84 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/14 ,  G11C16/08

CPC classification number: G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/06 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/792

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

公开(公告)号：US20180097007A1

公开(公告)日：2018-04-05

申请号：US15669595

申请日：2017-08-04

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kenichiro SONODA

IPC: H01L27/11568 ,  H01L29/78 ,  H01L27/11565 ,  H01L29/423

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: To provide a semiconductor device having improved reliability by preventing, in a split-gate MONOS memory comprised of a fin type transistor, unbalanced injection distribution of electrons into a charge accumulation film due to the shape of the fin. A memory gate electrode configuring a memory cell is formed over a fin. The impurity concentration of a portion of this memory gate electrode contiguous to an ONO film that covers the upper surface of the fin is made lower than that of a portion of the memory gate electrode contiguous to an ONO film that covers the side surface of the fin.

公开(公告)号：US20150111357A1

公开(公告)日：2015-04-23

申请号：US14586452

申请日：2014-12-30

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66 ,  H01L27/115

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability.First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

Abstract translation: 提供包括具有更高可靠性的存储单元的半导体器件的制造方法。 形成存储单元形成区域中的第一和第二堆叠结构，以在晶体管形成区域中具有比第三层叠结构更大的高度，然后形成层间绝缘层以覆盖这些堆叠结构，然后进行抛光。

公开(公告)号：US20240178222A1

公开(公告)日：2024-05-30

申请号：US18483737

申请日：2023-10-10

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Naohito SUZUMURA ,  Eiji TSUKUDA ,  Yoshiki YAMAMOTO

IPC: H01L27/06 ,  H01L29/04 ,  H01L29/36

CPC classification number: H01L27/0629 ,  H01L29/04 ,  H01L29/36 ,  H01L29/665

Abstract: A resistance element is comprised of a first semiconductor layer of an SOI substrate and a second semiconductor layer formed on the first semiconductor layer. The second semiconductor layer has first and second semiconductor portions spaced apart from each other. The first semiconductor layer has a first region on which the first semiconductor portion is formed, a second region on which the second semiconductor portion is formed, and a third region on which no epitaxial semiconductor layer is formed. Each of the first region and the second region further has a low concentration region located next to the third region. An impurity concentration of the low concentration region is lower than an impurity concentration of the third region. Each semiconductor portion has a middle concentration region located on the low concentration region. An impurity concentration of the middle concentration region is higher than that of the low concentration region.

公开(公告)号：US20230299197A1

公开(公告)日：2023-09-21

申请号：US17697393

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji TSUKUDA ,  Tohru KAWAI ,  Atsushi AMO

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

公开(公告)号：US20180040379A1

公开(公告)日：2018-02-08

申请号：US15597294

申请日：2017-05-17

Applicant: Renesas Electronics Corporation

Inventor： Kenichiro SONODA ,  Eiji TSUKUDA ,  Keiichi MAEKAWA

IPC: G11C16/10 ,  H01L27/11573 ,  H01L29/06 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  H01L27/11568 ,  H01L29/792

CPC classification number: G11C16/10 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3445 ,  G11C16/3459 ,  H01L21/84 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/792

Abstract: A semiconductor device is provided that is capable of reducing the possibility of change in state of memory elements formed over a semiconductor substrate with an insulating layer interposed therebetween. The semiconductor device includes nonvolatile memory elements and a bias circuit. Each of the nonvolatile memory elements includes a drain region and a source region arranged so as to sandwich a semiconductor region where a channel is formed, a gate electrode, and a charge storage layer arranged between the gate electrode and the semiconductor region. The nonvolatile memory elements are arranged over the semiconductor substrate with the insulating layer interposed therebetween. When electrons are stored in the charge storage layer, the bias circuit reduces the potential difference between the gate electrode and at least one of the drain region and source region in order to decrease holes stored in the channel of a nonvolatile memory element.

公开(公告)号：US20160093716A1

公开(公告)日：2016-03-31

申请号：US14877521

申请日：2015-10-07

Applicant: Renesas Electronics Corporation

Inventor： Eiji TSUKUDA ,  Kozo KATAYAMA ,  Kenichiro SONODA ,  Tatsuya KUNIKIYO

IPC: H01L29/66 ,  H01L27/115 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L27/115 ,  H01L27/11563 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/792

Abstract: To provide a manufacturing method of a semiconductor device including a memory cell having a higher reliability. First and second stacked structures in a memory cell formation region are formed so as to have a larger height than a third stacked structure in a transistor formation region, and then an interlayer insulating layer is formed so as to cover these stacked structures and then polished.

公开(公告)号：US20190006382A1

公开(公告)日：2019-01-03

申请号：US16045183

申请日：2018-07-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke TAKEUCHI ,  Eiji TSUKUDA ,  Kenichiro SONODA ,  Shibun TSUDA

IPC: H01L27/11573 ,  H01L29/423 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11565

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.

公开(公告)号：US20170345842A1

公开(公告)日：2017-11-30

申请号：US15682492

申请日：2017-08-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yosuke TAKEUCHI ,  Eiji TSUKUDA ,  Kenichiro SONODA ,  Shibun TSUDA

IPC: H01L27/11573 ,  H01L27/11565 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/11573 ,  H01L27/11565 ,  H01L29/42344 ,  H01L29/7851 ,  H01L29/792 ,  H01L2029/7857

Abstract: A semiconductor device includes a semiconductor substrate, an element isolation film, and a fin having side surfaces facing each other in a first direction of an upper surface and a main surface connecting the facing side surfaces and extending in a second direction orthogonal to the first direction. The device further includes a control gate electrode arranged over the side surface via a gate insulation film and extending in the first direction, and a memory gate electrode arranged over the side surface via another gate insulation film having a charge accumulation layer and extending in the first direction. Furthermore, an overlap length by which the memory gate electrode overlaps with the side surface is smaller than an overlap length by which the control gate electrode overlaps with the side surface in the direction orthogonal to the upper surface.