公开(公告)号：US20200066646A1

公开(公告)日：2020-02-27

申请号：US16668802

申请日：2019-10-30

Applicant: Renesas Electronics Corporation

Inventor： Toshikazu HANAWA ,  Kazuhide FUKAYA ,  Makoto KOSHIMIZU

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: An interlayer insulating film has via holes. A sidewall conductive layer is arranged along a sidewall surface of one via hole and contains one or more kinds selected from a group including tungsten, titanium, titanium nitride, tantalum and molybdenum. A second metal wiring layer is embedded in one via hole and contains aluminum. A plug layer is embedded in the other via hole and contains one or more kinds selected from the group including tungsten, titanium, titanium nitride, tantalum and molybdenum.

公开(公告)号：US20190067472A1

公开(公告)日：2019-02-28

申请号：US16036434

申请日：2018-07-16

Applicant: Renesas Electronics Corporation

Inventor： Makoto KOSHIMIZU ,  Komaki INDUE ,  Hideki NIWAYAMA

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L21/266 ,  H01L29/36 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/06

Abstract: A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.

公开(公告)号：US20240421166A1

公开(公告)日：2024-12-19

申请号：US18641596

申请日：2024-04-22

Applicant: Renesas Electronics Corporation

Inventor： Makoto KOSHIMIZU ,  Shigeki TSUBAKI

IPC: H01L27/144 ,  H01L21/762 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L31/02

Abstract: An anode region and a cathode region of a photodiode are formed in a semiconductor substrate. At a main surface of the semiconductor substrate, a plurality of first STI regions are formed on the cathode region, and an oxide film is formed between the plurality of first STI regions. A shield electrode is formed on the plurality of first STI regions and the oxide film. A thickness of each of the plurality of first STI regions is smaller than a thickness of second STI region.

公开(公告)号：US20240038888A1

公开(公告)日：2024-02-01

申请号：US18334763

申请日：2023-06-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7817 ,  H01L27/088 ,  H01L29/0615

Abstract: A semiconductor substrate includes an n-type substrate region, an n-type first semiconductor region and a second semiconductor region disposed at different positions on the n-type substrate region, an n-type buried layer formed on the n-type first semiconductor region and on the second semiconductor region, a p-type third semiconductor region and a p-type fourth semiconductor region formed on the n-type buried layer and spaced apart from each other, and an n-type fifth semiconductor region that reaches an upper surface of the semiconductor substrate from the n-type buried layer. The n-type buried layer, the n-type first semiconductor region, and the n-type substrate region are present under the p-type third semiconductor region and the n-type fifth semiconductor region. A first transistor is formed in an upper portion of the p-type third semiconductor region, and a second transistor is formed in an upper portion of the p-type fourth semiconductor region.

公开(公告)号：US20220376040A1

公开(公告)日：2022-11-24

申请号：US17717724

申请日：2022-04-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric film formed on the semiconductor substrate, a gate electrode formed on the gate dielectric film, a field plate portion which is integrally formed with the gate electrode, a step insulating film in contact with the field plate portion, a high dielectric constant film in contact with the step insulating film and having a higher dielectric constant than silicon.

公开(公告)号：US20200212176A1

公开(公告)日：2020-07-02

申请号：US16815636

申请日：2020-03-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Hideki NIWAYAMA ,  Kazuyuki UMEZU ,  Hiroki SOEDA ,  Atsushi TACHIGAMI ,  Takeshi IIJIMA

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

Abstract: A terrace insulating film (SL) to be overridden by a gate electrode (G) of an nLDMOS device is configured by LOCOS, and a device isolation portion (SS) is configured by STI. Furthermore, on an outermost periphery of an active region where a plurality of nLDMOS devices are formed, a guard ring having the same potential as that of a drain region (D) is provided. And, via this guard ring, the device isolation portion (SS) is formed in a periphery of the active region, thereby not connecting but isolating the terrace insulating film (SL) and the device isolation portion (SS) from each other.