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    SEMICONDUCTOR DEVICE
    12.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20140239311A1

    公开(公告)日：2014-08-28

    申请号：US14188462

    申请日：2014-02-24

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

    IPC: H01L29/778 ,  H01L29/20

    CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

    Abstract: A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

    Abstract translation: 半导体器件包括缓冲层，沟道层和在衬底上形成的势垒层，穿过势垒层的沟槽到达沟道层的中间，以及通过栅极绝缘膜设置在沟槽内的栅电极。 沟道层含有n型杂质，位于缓冲层侧的沟道层的区域的n型杂质浓度大于位于势垒层侧的沟道层的区域，并且形成缓冲层 的氮化物半导体具有比沟道层宽的带隙。 沟道层由GaN制成，缓冲层由AlGaN制成。 沟道层具有含有中等浓度的n型杂质的沟道下层和形成在其上的主沟道层并且含有低浓度的n型杂质。

    Semiconductor device
    13.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09941284B2

    公开(公告)日：2018-04-10

    申请号：US15657690

    申请日：2017-07-24

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru Kawai ,  Masahiro Shimizu

    IPC: H01L27/092 ,  G11C11/419

    CPC classification number: H01L27/0928 ,  G11C11/419 ,  H01L27/1104 ,  H01L28/00

    Abstract: A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.

    Semiconductor device
    14.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US09748247B2

    公开(公告)日：2017-08-29

    申请号：US15359729

    申请日：2016-11-23

    Applicant: Renesas Electronics Corporation

    Inventor： Tohru Kawai ,  Masahiro Shimizu

    IPC: H01L27/00 ,  H01L27/092 ,  G11C11/419

    CPC classification number: H01L27/0928 ,  G11C11/419 ,  H01L27/1104 ,  H01L28/00

    Abstract: A semiconductor device aims to prevent a leak current from flowing between a well and a corner of an active region formed on an upper surface of another well in an SRAM. In a memory cell of the SRAM, a load MOSFET is formed. An end of an active region extending in y-direction is arranged to gradually go away from a p-well as it goes from a gate electrode G2 side to a gate electrode G4 side in such a manner that a distance in x-direction between the end of the active region and the p-well is larger than a shortest distance in the x-direction between the p-well and the active region.

    Semiconductor device
    15.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US12165993B2

    公开(公告)日：2024-12-10

    申请号：US17108298

    申请日：2020-12-01

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Tohru Kawai ,  Yasutaka Nakashiba

    IPC: H01L23/64 ,  H01F27/00

    Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

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