公开(公告)号：US10236371B2

公开(公告)日：2019-03-19

申请号：US15403539

申请日：2017-01-11

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522 ,  H01L23/00

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US11232990B2

公开(公告)日：2022-01-25

申请号：US17121175

申请日：2020-12-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yuta Mizukami ,  Tohru Kawai

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/49 ,  H01L21/225

Abstract: A semiconductor device includes a semiconductor substrate, an insulating layer, a semiconductor layers and a silicide layer. The insulating layer is formed on the semiconductor substrate. The semiconductor layer is formed on the insulating layer and includes a polycrystalline silicon. The silicide layer is formed on the semiconductor layer. The semiconductor layer has a first semiconductor part and a second semiconductor part. The first semiconductor part includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type. The second semiconductor part is adjacent the second semiconductor region. In a width direction of the first semiconductor part, a second length of the second semiconductor part is greater than a first length of the first semiconductor part. A distance between the first and second semiconductor regions is 100 nm or more in an extension direction in which the first semiconductor region extends.

公开(公告)号：US10921515B2

公开(公告)日：2021-02-16

申请号：US16681372

申请日：2019-11-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki ,  Tohru Kawai

IPC: G02B6/12 ,  G02B6/13 ,  G02F1/025 ,  G02B6/42

Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.

公开(公告)号：US10416481B2

公开(公告)日：2019-09-17

申请号：US16182259

申请日：2018-11-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru Kawai ,  Shinichi Watanuki ,  Yasutaka Nakashiba

IPC: G02F1/025

Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.

公开(公告)号：US08963207B2

公开(公告)日：2015-02-24

申请号：US14188462

申请日：2014-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L21/768 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

Abstract translation: 半导体器件包括缓冲层，沟道层和在衬底上形成的势垒层，穿过势垒层的沟槽到达沟道层的中间，以及通过栅极绝缘膜设置在沟槽内的栅电极。 沟道层含有n型杂质，位于缓冲层侧的沟道层的区域的n型杂质浓度大于位于势垒层侧的沟道层的区域，并且形成缓冲层 的氮化物半导体具有比沟道层宽的带隙。 沟道层由GaN制成，缓冲层由AlGaN制成。 沟道层具有含有中等浓度的n型杂质的沟道下层和形成在其上的主沟道层并且含有低浓度的n型杂质。

公开(公告)号：US12040399B2

公开(公告)日：2024-07-16

申请号：US17697393

申请日：2022-03-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Eiji Tsukuda ,  Tohru Kawai ,  Atsushi Amo

IPC: H01L29/51 ,  H01L29/78

CPC classification number: H01L29/78391 ,  H01L29/516

Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.

公开(公告)号：US11112624B2

公开(公告)日：2021-09-07

申请号：US16601280

申请日：2019-10-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Tohru Kawai

IPC: G02F1/025 ,  H01L23/48 ,  G02F1/225 ,  G02B6/12

Abstract: A semiconductor device includes a first insulating layer, an optical waveguide, a first slab portion, a second insulating layer, and a conductive layer. The optical waveguide is formed on the first insulating layer and has a first side surface and a second side surface. The first slab portion is adjacent to the first side surface. The second insulating layer is formed on the optical waveguide. The conductive layer is formed on the second insulating layer. The optical waveguide has a first conductivity type. The first slab portion has first portion, second portion and third portion. The first portion has a second conductivity type opposite to the first conductivity type. The second portion is located farther from the optical waveguide than the first portion and has a first conductivity type. The third portion is formed between the optical waveguide and the second portion and has the first conductivity type.

公开(公告)号：US10475918B2

公开(公告)日：2019-11-12

申请号：US16263256

申请日：2019-01-31

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/07 ,  H01L29/06 ,  H01L29/10 ,  H01L23/495 ,  H01L23/522 ,  H01L23/482 ,  H01L23/00

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US09933568B2

公开(公告)日：2018-04-03

申请号：US15363663

申请日：2016-11-29

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba

IPC: G02B6/122 ,  H01L21/265 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/36 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B2006/12061 ,  G02B2006/12123 ,  G02B2006/12142 ,  G02B2006/12176 ,  H01L21/26506 ,  H01L21/76898 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/36

Abstract: Provided is an SOI substrate which has a substrate, an insulating layer formed over the substrate, and a semiconductor layer formed over the insulating layer. Optical waveguides are formed in the semiconductor layer of the SOI substrate. This substrate has a low resistance semiconductor layer and a high resistance semiconductor layer thereover. Further, wirings which are formed through insulating films are provided on the optical waveguides. In this manner, the low resistance semiconductor layer is arranged in the surface part of the substrate of the insulating films, thereby restraining an eddy current generated in the substrate due to an electric signal transmitted through the wirings.

公开(公告)号：US09564426B2

公开(公告)日：2017-02-07

申请号：US14931991

申请日：2015-11-04

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Yasutaka Nakashiba ,  Yutaka Akiyama

IPC: H01L27/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L27/07 ,  H01L23/00

CPC classification number: H01L29/7813 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

Abstract translation: 提高半导体器件的性能而不增加半导体芯片的面积尺寸。 例如，功率晶体管的源电极和电容器元件的上电极具有重叠部分。 换句话说，电容器元件的上电极通过电容器绝缘膜形成在功率晶体管的源极上。 也就是说，功率晶体管和电容器元件以半导体芯片的厚度方向层叠的方式配置。 结果，可以在抑制半导体芯片的平面尺寸的增加的同时添加电耦合到功率晶体管的电容器元件。