公开(公告)号：US09984884B2

公开(公告)日：2018-05-29

申请号：US15385507

申请日：2016-12-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/04 ,  H01L29/778 ,  H01L21/28 ,  H01L21/02 ,  H01L21/308 ,  H01L29/423 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer, forming thereover a second nitride semiconductor layer having a band gap wider than that of the first nitride semiconductor layer, and thereby forming a stacked body, etching the stacked body with a first film placed over the stacked body and including a first opening portion as a mask to form a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, causing an end portion of the first film to retreat from an end portion of the trench, forming a second film over the first film including the inside of the trench, and forming a gate electrode over the second film.

公开(公告)号：US09660045B2

公开(公告)日：2017-05-23

申请号：US15079879

申请日：2016-03-24

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Toshiyuki Takewaki ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/51 ,  H01L29/778 ,  H01L29/66 ,  H01L29/205 ,  H01L29/20 ,  H01L23/29 ,  H01L23/31 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

公开(公告)号：US09231096B2

公开(公告)日：2016-01-05

申请号：US14550118

申请日：2014-11-21

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Yuji Ando ,  Tatsuo Nakayama ,  Takashi Inoue ,  Kazuki Ota

IPC: H01L29/00 ,  H01L29/778 ,  H01L29/205 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423 ,  H01L29/201 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/517 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1−zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1−xN (0≦x≦1) or InyGa1−yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.

Abstract translation: 场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。 或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上， 位于源电极和漏电极之间的区域。

公开(公告)号：US10410868B2

公开(公告)日：2019-09-10

申请号：US15882687

申请日：2018-01-29

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/778 ,  H01L29/51 ,  H01L29/40 ,  H01L29/20 ,  H01L21/02 ,  H01L21/308 ,  H01L29/45

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer and having a band gap wider than a band gap of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer and reaching an inside of the first nitride semiconductor layer, a gate electrode placed in the trench over a gate insulating film, and a first electrode and a second electrode formed over the second nitride semiconductor layer on both sides of the gate electrode, respectively.

公开(公告)号：US09520489B2

公开(公告)日：2016-12-13

申请号：US14604796

申请日：2015-01-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/522 ,  H01L29/15 ,  H01L29/417 ,  H01L29/861 ,  H01L27/06 ,  H01L29/423 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

Abstract translation: 提高了半导体器件的特性。 半导体器件被配置为提供穿透阻挡层的沟槽，并且到达n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分，其中 形成在基板上方，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分彼此电耦合。 p型层和源电极通过到达p型层的连接部分彼此电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

公开(公告)号：US09502551B2

公开(公告)日：2016-11-22

申请号：US14829216

申请日：2015-08-18

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/205

CPC classification number: H01L29/7787 ,  H01L21/02458 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alxα1-xN layer (α includes Ga or In, and 0

Abstract translation: 半导体器件包括第一半导体层，形成在第一半导体层上的第二半导体层，与第二半导体层接触的栅极绝缘膜，以及经由栅极绝缘膜与第二半导体层相对的栅电极。 第一半导体层包括Al xα1-x N层（α包括Ga或In，0

公开(公告)号：US20150145004A1

公开(公告)日：2015-05-28

申请号：US14548527

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Toshiyuki Takewaki ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/51 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Abstract translation: 改善了半导体器件的特性。 半导体器件形成为具有在衬底，阻挡层，在开口区域中穿过阻挡层的沟槽并且到达沟道层的某一点的沟槽层，布置在沟槽中的栅极电极 栅极绝缘膜，以及形成在开口区域外侧的阻挡层上的绝缘膜。 然后，绝缘膜具有富Si硅氮化膜和位于其下方的富氮氮化硅膜的叠层结构。 因此，将绝缘膜的上层设定为富Si硅氮化膜。 这使得能够提高击穿电压，并且还能够提高耐蚀刻性。 而绝缘膜的下层被设定为富N的氮化硅膜。 这可以抑制崩溃。

公开(公告)号：US08963207B2

公开(公告)日：2015-02-24

申请号：US14188462

申请日：2014-02-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L21/768 ,  H01L29/36 ,  H01L29/66 ,  H01L29/10 ,  H01L29/20 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device includes a buffer layer, a channel layer and a barrier layer formed over a substrate, a trench penetrating through the barrier layer to reach the middle of the channel layer, and a gate electrode disposed inside the trench via a gate insulating film. The channel layer contains n-type impurities, and a region of the channel layer positioned on a buffer layer side has an n-type impurity concentration larger than a region of the channel layer positioned on a barrier layer side, and the buffer layer is made of nitride semiconductor having a band gap wider than that of the channel layer. The channel layer is made of GaN and the buffer layer is made of AlGaN. The channel layer has a channel lower layer containing n-type impurities at an intermediate concentration and a main channel layer formed thereon and containing n-type impurities at a low concentration.

Abstract translation: 半导体器件包括缓冲层，沟道层和在衬底上形成的势垒层，穿过势垒层的沟槽到达沟道层的中间，以及通过栅极绝缘膜设置在沟槽内的栅电极。 沟道层含有n型杂质，位于缓冲层侧的沟道层的区域的n型杂质浓度大于位于势垒层侧的沟道层的区域，并且形成缓冲层 的氮化物半导体具有比沟道层宽的带隙。 沟道层由GaN制成，缓冲层由AlGaN制成。 沟道层具有含有中等浓度的n型杂质的沟道下层和形成在其上的主沟道层并且含有低浓度的n型杂质。

公开(公告)号：US20140353720A1

公开(公告)日：2014-12-04

申请号：US14271277

申请日：2014-05-06

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hiroshi Kawaguchi ,  Toshiyuki Takewaki ,  Nobuhiro Nagura ,  Takayuki Nagai ,  Yoshinao Miura ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/28264 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/308 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/452 ,  H01L29/513 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7787 ,  H01L29/7827

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has a substrate and thereon a buffer layer, a channel layer, a barrier layer, a trench penetrating therethrough and reaching the inside of the channel layer, a gate electrode placed in the trench via a gate insulating film, and drain and source electrodes on the barrier layer on both sides of the gate electrode. The gate insulating film has a first portion made of a first insulating film and extending from the end portion of the trench to the side of the drain electrode and a second portion made of first and second insulating films and placed on the side of the drain electrode relative to the first portion. The on resistance can be reduced by decreasing the thickness of the first portion at the end portion of the trench on the side of the drain electrode.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件具有衬底，其上具有缓冲层，沟道层，阻挡层，穿透其中并到达沟道层内部的沟槽，通过栅极绝缘膜放置在沟槽中的栅电极，以及漏极和源极 位于栅电极两侧的阻挡层上的电极。 栅极绝缘膜具有由第一绝缘膜形成并从沟槽的端部延伸至漏极侧的第一部分和由第一绝缘膜和第二绝缘膜构成的第二部分，并且设置在漏电极侧 相对于第一部分。 可以通过减小在漏电极侧的沟槽的端部处的第一部分的厚度来减小导通电阻。

公开(公告)号：US10014403B2

公开(公告)日：2018-07-03

申请号：US15437559

申请日：2017-02-21

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/15 ,  H01L29/201 ,  H01L21/027 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/205 ,  H01L29/10 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/0274 ,  H01L21/3065 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/402 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786

Abstract: A semiconductor device includes a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed over the first nitride semiconductor layer, a third nitride semiconductor layer formed over the second nitride semiconductor layer, a fourth nitride semiconductor layer formed over the third nitride semiconductor layer, a trench that penetrates the fourth nitride semiconductor layer and reaches as far as the third nitride semiconductor layer, a gate electrode disposed by way of a gate insulation film in the trench, a first electrode and a second electrode formed respectively over the fourth nitride semiconductor layer on both sides of the gate electrode, and a coupling portion for coupling the first electrode and the first nitride semiconductor layer.