公开(公告)号：US12165993B2

公开(公告)日：2024-12-10

申请号：US17108298

申请日：2020-12-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tohru Kawai ,  Yasutaka Nakashiba

IPC: H01L23/64 ,  H01F27/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating layer, a first inductor, a second insulating layer, a second inductor, a pad and an annular wiring. The first insulating layer is formed on the semiconductor substrate. The first inductor is directly formed on the first insulating layer. The second insulating layer is formed on the first insulating layer such that the second insulating layer covers the first inductor. The second inductor is directly formed on the second insulating layer such that the second inductor faces the first inductor. The pad is directly formed on the second insulating layer. The pad is electrically connected with the second inductor. The annular wiring is electrically connected with the pad. The annular wiring is spaced apart from the second inductor. The annular wiring surrounds the second inductor without forming a vertex in plan view.

公开(公告)号：US11830944B2

公开(公告)日：2023-11-28

申请号：US17380682

申请日：2021-07-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto Koshimizu ,  Yasutaka Nakashiba

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/045 ,  H01L29/66681

Abstract: The source region, drain region, buried insulating film, gate insulating film, and gate electrode of the semiconductor device are formed in a main surface of a semiconductor substrate. The buried insulating film is buried in a first trench formed between the source and drain regions. The first trench has a first side surface and a first bottom surface. The first side surface faces the source region in a first direction extending from one of the source and drain regions to the other. The first bottom surface is connected to the first side surface and is along the main surface of the semiconductor substrate. A crystal plane of a first surface of the semiconductor substrate, which is the first side surface of the first trench, is (111) plane. A crystal plane of a second surface of the semiconductor substrate, which is the bottom surface of the first trench, is (100) plane.

公开(公告)号：US11756881B2

公开(公告)日：2023-09-12

申请号：US17231623

申请日：2021-04-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Uchida ,  Yasutaka Nakashiba ,  Shinichi Kuwabara

IPC: H01L23/522 ,  H01F27/28 ,  H01L23/00

CPC classification number: H01L23/5227 ,  H01F27/2804 ,  H01L23/5226 ,  H01L24/48 ,  H01L2224/48137

Abstract: A semiconductor device includes: a first substrate; a multilayer wiring layer formed on the first substrate; a first inductor formed into a meander shape on the multilayer wiring layer in a plan view; and a second inductor formed into a meander shape on the multilayer wiring layer in a plain view, and arranged so as to be close to the first inductor in a plan view and not to overlap with the first inductor. A transformer is configured by the first inductor and the second inductor and, in a plan view, the first inductor and the second inductor extend along a first direction in which one side of the first substrate extends.

公开(公告)号：US11630270B2

公开(公告)日：2023-04-18

申请号：US16811959

申请日：2020-03-06

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/42

Abstract: A semiconductor device includes a cladding layer and a first optical waveguide. The first optical waveguide is formed on the first cladding layer. An end surface of the first optical waveguide is inclined relative to a vertical line perpendicular to an upper surface of the cladding layer.

公开(公告)号：US11262500B2

公开(公告)日：2022-03-01

申请号：US16700580

申请日：2019-12-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba ,  Seigo Namioka ,  Tomoo Nakayama

IPC: G02B6/122 ,  G02B6/13 ,  G02F1/025 ,  G02B6/12

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a second surface opposite to the first surface, and having a first recess portion formed on the first surface, a first cladding layer located in the first recess portion, and a first optical waveguide formed on the first cladding layer. The first optical waveguide overlaps with the first cladding layer in plan view.

公开(公告)号：US11137560B2

公开(公告)日：2021-10-05

申请号：US16408100

申请日：2019-05-09

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/42 ,  H01L23/00 ,  H04B10/80 ,  H01L25/16

Abstract: The semiconductor module includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip includes an optical device such as an optical waveguide and wiring formed over the optical device. The second semiconductor chip include semiconductor elements such as MISFET, and wiring formed over the semiconductor elements. A top surface of the first semiconductor chip is laminated with a top surface of the second semiconductor chip such that the first and second wirings are directly contacted with each other.

公开(公告)号：US11079540B2

公开(公告)日：2021-08-03

申请号：US16183319

申请日：2018-11-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Watanuki ,  Yasutaka Nakashiba

IPC: G02F1/035 ,  G02F1/295 ,  G02B6/10 ,  G02B6/122 ,  H01L23/532 ,  H01L25/16 ,  H01L21/02 ,  G02F1/025 ,  G02B6/12 ,  H01L23/34 ,  G02B6/43

Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.

公开(公告)号：US11079539B2

公开(公告)日：2021-08-03

申请号：US16370409

申请日：2019-03-29

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya Iida ,  Yasutaka Nakashiba

IPC: G02B6/12 ,  H01S5/02345 ,  H01L31/12 ,  H01L31/0232 ,  H01L31/18 ,  H01S5/02326 ,  H01S5/02 ,  H01S5/026 ,  H01S5/40 ,  H01S5/02375 ,  H01S5/042 ,  H01S5/028 ,  H01L31/02

Abstract: According to the present invention, a first semiconductor chip includes a semiconductor substrate, an optical waveguide formed on an upper surface of the semiconductor substrate, and a concave portion formed in the semiconductor substrate in a region that differs from a region in which the optical waveguide is formed. A second semiconductor chip includes a compound semiconductor substrate, and a light emitting unit formed on an upper surface of the compound semiconductor substrate and emitting a laser beam. The second semiconductor chip is mounted in the concave portion of the first semiconductor chip, and a pedestal which is an insulating film is formed between a bottom surface of the concave portion and a back surface of the compound semiconductor substrate.

公开(公告)号：US10720411B2

公开(公告)日：2020-07-21

申请号：US16278927

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi Kuwabara ,  Yasutaka Nakashiba ,  Tetsuya Iida

IPC: H01L27/08 ,  H01L25/065 ,  H02K11/33 ,  H01L23/31 ,  H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L49/02 ,  H01L23/522

Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

公开(公告)号：US10578805B2

公开(公告)日：2020-03-03

申请号：US16183433

申请日：2018-11-07

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka Nakashiba ,  Shinichi Watanuki

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/13 ,  G02B6/12

Abstract: An optical waveguide formed at the same layer as that of a microscopic optical device and a spot size converter largely different in size are integrally formed. A semiconductor device has an optical waveguide part functioning as a spot size converter. The optical waveguide part includes a plurality of optical waveguide bodies penetrating through an interlayer insulation layer in the thickness direction.