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    Memory controller with staggered request signal output
    11.
    发明授权
    Memory controller with staggered request signal output 有权
    具有交错请求信号输出的存储控制器

    公开(公告)号：US08638637B2

    公开(公告)日：2014-01-28

    申请号：US13720720

    申请日：2012-12-19

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

    IPC: G11C8/00

    CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

    Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

    Strobe Acquisition and Tracking
    14.
    发明申请
    Strobe Acquisition and Tracking 审中-公开

    公开(公告)号：US20180082725A1

    公开(公告)日：2018-03-22

    申请号：US15665312

    申请日：2017-07-31

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G11C7/22 ,  G06F13/16 ,  G11C7/02

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Strobe acquisition and tracking
    17.
    发明授权
    Strobe acquisition and tracking 有权
    频闪采集和跟踪

    公开(公告)号：US09257163B2

    公开(公告)日：2016-02-09

    申请号：US13959633

    申请日：2013-08-05

    Applicant: Rambus Inc.

    Inventor： Bret Stott ,  Frederick A. Ware ,  Ian P. Shaeffer ,  Yuanlong Wang

    IPC: G06F12/00 ,  G11C7/22 ,  G06F13/16 ,  G11C7/02

    CPC classification number: G11C7/222 ,  G06F13/1689 ,  G11C7/02 ,  G11C7/22

    Abstract: A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.

    Abstract translation: 存储器控制器包括用于接收数据选通信号和对应的读取数据的接口。 数据选通信号和读取数据对应于由存储器控制器发出的读取命令，并且根据数据选通信号和使能信号接收读取的数据。 存储器控制器中的电路是动态地调整使能信号和数据选通信号之间的定时偏移，并且控制逻辑将根据从自由信号发出的最后读取命令以来的时间间隔的确定发出补充读取命令 存储器控制器超过预定值。

    Memory controller with staggered request signal output
    19.
    发明授权
    Memory controller with staggered request signal output 有权
    具有交错请求信号输出的存储控制器

    公开(公告)号：US09165617B2

    公开(公告)日：2015-10-20

    申请号：US14153822

    申请日：2014-01-13

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

    IPC: G11C7/00 ,  G11C7/10 ,  G06F13/16 ,  G06F12/00

    CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

    Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

    MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT
    20.
    发明申请
    MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT 有权
    存储器控制器，具有需要的信号输出

    公开(公告)号：US20140173240A1

    公开(公告)日：2014-06-19

    申请号：US14153822

    申请日：2014-01-13

    Applicant: Rambus Inc.

    Inventor： Ian P. Shaeffer ,  Bret Stott ,  Benedict C. Lau

    IPC: G06F13/16 ,  G11C7/10

    CPC classification number: G11C7/1063 ,  G06F12/00 ,  G06F13/1689 ,  G11C7/1072

    Abstract: A memory controller having a time-staggered request signal output. A first timing signal is generated while a second timing signal is generated having a first phase difference relative to the first timing signal. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

    Abstract translation: 具有时间交错请求信号输出的存储器控​​制器。 产生第一定时信号，同时产生具有相对于第一定时信号的第一相位差的第二定时信号。 响应于第一定时信号发送地址值，响应于构成第一存储器访问请求的第二定时信号，地址值和控制值发送控制值。

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