公开(公告)号：US11853600B2

公开(公告)日：2023-12-26

申请号：US17235629

申请日：2021-04-20

Applicant: Rambus Inc.

Inventor： Frederick A Ware ,  Scott C. Best

IPC: G06F13/00 ,  G06F3/06 ,  G11C5/04 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/0673 ,  G06F13/1673 ,  G11C5/04 ,  Y02D10/00

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US11646090B2

公开(公告)日：2023-05-09

申请号：US17245491

申请日：2021-04-30

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/00 ,  G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

CPC classification number: G11C29/24 ,  G06F11/1008 ,  G11C29/50016 ,  G11C5/04 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US11011248B2

公开(公告)日：2021-05-18

申请号：US16690743

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/00 ,  G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C5/04 ,  G11C29/44

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20170337984A1

公开(公告)日：2017-11-23

申请号：US15626040

申请日：2017-06-16

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G11C29/50 ,  G06F11/10 ,  G11C29/44 ,  G11C5/04

CPC classification number: G06F11/1008 ,  G11C5/04 ,  G11C29/24 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US20170242807A1

公开(公告)日：2017-08-24

申请号：US15428121

申请日：2017-02-08

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/16 ,  G06F9/48 ,  G06F13/40 ,  G11C11/4094 ,  G11C11/4076

CPC classification number: G06F13/1673 ,  G06F9/4881 ,  G06F13/1678 ,  G06F13/4059 ,  G06F2209/486 ,  G06F2209/5018 ,  G11C11/4076 ,  G11C11/4094

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US12197354B2

公开(公告)日：2025-01-14

申请号：US18239689

申请日：2023-08-29

Applicant: Rambus Inc.

Inventor： Hongzhong Zheng ,  Frederick A Ware

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4094 ,  H04L47/50

Abstract: A method of transferring data between a memory controller and at least one memory module via a primary data bus having a primary data bus width is disclosed. The method includes accessing a first one of a memory device group via a corresponding data bus path in response to a threaded memory request from the memory controller. The accessing results in data groups collectively forming a first data thread transferred across a corresponding secondary data bus path. Transfer of the first data thread across the primary data bus width is carried out over a first time interval, while using less than the primary data transfer continuous throughput during that first time interval. During the first time interval, at least one data group from a second data thread is transferred on the primary data bus.

公开(公告)号：US12148462B2

公开(公告)日：2024-11-19

申请号：US18511747

申请日：2023-11-16

Applicant: Rambus Inc.

Inventor： Frederick A Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/22 ,  G11C11/4076

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20240144992A1

公开(公告)日：2024-05-02

申请号：US18511747

申请日：2023-11-16

Applicant: Rambus Inc.

Inventor： Frederick A Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/408 ,  G06F12/06 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4082 ,  G06F12/06 ,  G06F13/1673 ,  G06F13/1684 ,  G11C5/04 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4093 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US20230377668A1

公开(公告)日：2023-11-23

申请号：US18138661

申请日：2023-04-24

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Frederick A Ware ,  Suresh Rajan ,  Thomas Vogelsang

IPC: G11C29/24 ,  G06F11/10 ,  G11C29/50 ,  G11C29/44 ,  G11C5/04

CPC classification number: G11C29/24 ,  G06F11/1008 ,  G11C29/50016 ,  G11C2029/4402 ,  G11C2211/4061 ,  G11C5/04

Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

公开(公告)号：US11314681B2

公开(公告)日：2022-04-26

申请号：US16874439

申请日：2020-05-14

Applicant: Rambus Inc.

Inventor： Frederick A Ware

IPC: G06F13/42

Abstract: An integrated circuit device is disclosed including core circuitry and interface circuitry. The core circuitry outputs in parallel a set of data bits, while the interface circuitry couples to the core circuitry. The interface circuitry receives in parallel a first number of data bits among the set of data bits from the core circuitry and outputs in parallel a second number of data bits. The ratio of the first number to the second number is a non-power-of-2 value.