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11.发明申请Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System 有权在多处理器系统中处理多个存储器请求的方法和装置公开(公告)号：US20090198933A1
公开(公告)日：2009-08-06
申请号：US12024181
申请日：2008-02-01
IPC分类号： G06F12/14
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译： 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。 然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。
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12.发明申请DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING MULTIPLE PLANES OF PROCESSING NODES 审中-公开数据处理系统，方法和互连织物支持多个加工点的平面公开(公告)号：US20080225863A1
公开(公告)日：2008-09-18
申请号：US12124639
申请日：2008-05-21
IPC分类号： H04L12/56
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。
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13.发明授权Binding a process to a special purpose processing element having characteristics of a processor 有权将过程绑定到具有处理器特征的专用处理元件公开(公告)号：US08893126B2
公开(公告)日：2014-11-18
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, and power perspective. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译： 提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。 为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于 例。 异构处理元素模型将特殊处理元素与编程角度，操作系统角度和功能视角相结合，将处理器与处理器相同。 操作系统可以使用安全引擎，例如，与处理器相同。
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14.发明申请Processing Units Within a Multiprocessor System Adapted to Support Memory Locks 审中-公开适用于支持内存锁的多处理器系统中的处理单元公开(公告)号：US20090198920A1
公开(公告)日：2009-08-06
申请号：US12024234
申请日：2008-02-01
IPC分类号： G06F12/00
CPC分类号： G06F15/16 , G06F9/3004 , G06F9/30087 , G06F9/526
摘要： A processing unit within a multiprocessor system adapted to support memory locks is disclosed. In response to a request for accessing a data block being denied when a lock control section of the data block has been set by a memory controller, a timer countdown is started within a processing unit within a multiprocessor system. The requesting processing unit can relinquish the access request once the timer countdown has reached a timeout period.
摘要翻译： 公开了一种适于支持存储器锁的多处理器系统内的处理单元。 响应于当由存储器控制器设置数据块的锁定控制部分时访问被拒绝的数据块的请求，在多处理器系统内的处理单元内启动定时器倒计时。 一旦定时器倒计时达到超时时间，请求处理单元可以放弃访问请求。
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15.发明申请Method and Apparatus for Supporting Low-Overhead Memory Locks Within a Multiprocessor System 审中-公开用于支持多处理器系统内的低成本内存锁的方法和装置公开(公告)号：US20090198916A1
公开(公告)日：2009-08-06
申请号：US12024223
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Edward J. Seminaro , William J. Starke
IPC分类号： G06F12/14
CPC分类号： G06F12/1466 , G06F9/3004 , G06F9/30087
摘要： A method for supporting low-overhead memory locks within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is ignored. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译： 公开了一种用于支持多处理器系统内的低开销存储器锁的方法。 锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。 响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。 如果已经设置了数据块的锁定控制部分，则忽略访问数据块的请求。 否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。
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16.发明授权Data processing system, processor and method of data processing that support memory access according to diverse memory models 失效数据处理系统，处理器和数据处理方法，根据不同的内存模型支持内存访问公开(公告)号：US07610458B2
公开(公告)日：2009-10-27
申请号：US11380018
申请日：2006-04-25
CPC分类号： G06F13/1631 , G06F12/0811 , G06F12/0815 , G06F12/0846 , G06F12/0888
摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.
摘要翻译： 数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。 数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。 访问内存子系统的存储操作与第一个设置或第二个设置相关联。 数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成 在同步操作之后的存储操作之前。
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公开(公告)号：US20090198849A1
公开(公告)日：2009-08-06
申请号：US12024169
申请日：2008-02-01
IPC分类号： G06F12/14
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087 , G06F17/30171 , G06F17/30362
摘要： A memory lock mechanism within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory of the multiprocessor system. In response to a request for accessing the data block by a processing unit within the multiprocessor system, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the request for accessing the data block is denied. Otherwise, if the lock control section of the data block has not been set, the lock control section of the data block is set, and the request for accessing the data block is allowed.
摘要翻译： 公开了一种多处理器系统内的存储锁定机构。 锁控制部分最初被分配给多处理器系统的系统存储器内的数据块。 响应于由多处理器系统内的处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已被设置。 如果已经设置了数据块的锁定控制部分，则拒绝访问数据块的请求。 否则，如果未设置数据块的锁定控制部分，则设置数据块的锁定控制部分，并且允许访问数据块的请求。
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18.发明申请Method and Apparatus for Supporting Distributed Computing Within a Multiprocessor System 审中-公开在多处理器系统中支持分布式计算的方法和装置公开(公告)号：US20090198695A1
公开(公告)日：2009-08-06
申请号：US12024245
申请日：2008-02-01
IPC分类号： G06F17/30
CPC分类号： G06F9/526 , G06F9/3004 , G06F9/30087
摘要： A locking mechanism for supporting distributed computing within a multiprocessor system is disclosed. A lock control section and a stage control section are assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made by a memory controller whether or not the lock control section of the data block has been set. If the lock control section of the data block has been set, the access request is denied. Otherwise, if the lock control section of the data block has not been set, another determination is made whether or not a current processing stage of the requesting processing unit matches a processing stage indicated by the stage control section. If the current processing stage of the requesting processing unit does not match the processing stage indicated by the stage control section, the access request is denied; otherwise, the access request is allowed.
摘要翻译： 公开了一种用于在多处理器系统内支持分布式计算的锁定机构。 锁定控制部分和级控制部分被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，由存储器控制器确定数据块的锁定控制部分是否已经被设置。 如果数据块的锁定控制部分已设置，则访问请求被拒绝。 否则，如果数据块的锁定控制部分未被设置，则另外确定请求处理单元的当前处理级是否与由级控制部分指示的处理级相匹配。 如果请求处理单元的当前处理阶段与舞台控制部分指示的处理阶段不匹配，则拒绝该访问请求; 否则，允许访问请求。
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19.发明授权Method and apparatus for handling multiple memory requests within a multiprocessor system 有权用于在多处理器系统内处理多个存储器请求的方法和装置公开(公告)号：US08214603B2
公开(公告)日：2012-07-03
申请号：US12024181
申请日：2008-02-01
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译： 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。 然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。
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20.发明授权Data processing system, method and interconnect fabric supporting multiple planes of processing nodes 有权支持多个处理节点平面的数据处理系统，方法和互连结构公开(公告)号：US07818388B2
公开(公告)日：2010-10-19
申请号：US11245887
申请日：2005-10-07
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。
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