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1.发明授权Data processing system, processor and method of data processing that support memory access according to diverse memory models 失效数据处理系统，处理器和数据处理方法，根据不同的内存模型支持内存访问公开(公告)号：US07610458B2
公开(公告)日：2009-10-27
申请号：US11380018
申请日：2006-04-25
CPC分类号： G06F13/1631 , G06F12/0811 , G06F12/0815 , G06F12/0846 , G06F12/0888
摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.
摘要翻译： 数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。 数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。 访问内存子系统的存储操作与第一个设置或第二个设置相关联。 数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成 在同步操作之后的存储操作之前。
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2.发明授权Data processing system, processor and method of data processing that reduce store queue entry utilization for synchronizing operations 失效数据处理系统，处理器和数据处理方法，减少存储队列入口利用率，用于同步操作公开(公告)号：US07454580B2
公开(公告)日：2008-11-18
申请号：US11380020
申请日：2006-04-25
申请人： Ravi K. Arimilli , Thomas M. Capasso , Robert A. Cargnoni , Guy L. Guthrie , Hugh Shen , William J. Starke
发明人： Ravi K. Arimilli , Thomas M. Capasso , Robert A. Cargnoni , Guy L. Guthrie , Hugh Shen , William J. Starke
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/544
摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.
摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。
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3.发明授权公开(公告)号：US08332588B2
公开(公告)日：2012-12-11
申请号：US13349315
申请日：2012-01-12
IPC分类号： G06F12/04
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。
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4.发明申请PERFORMING A PARTIAL CACHE LINE STORAGE-MODIFYING OPERATION BASED UPON A HINT 失效根据提示执行部分缓存线存储 - 修改操作公开(公告)号：US20120265938A1
公开(公告)日：2012-10-18
申请号：US13349315
申请日：2012-01-12
IPC分类号： G06F12/08
CPC分类号： G06F12/0822
摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.
摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。
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5.发明授权Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains 有权处理器，数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法公开(公告)号：US07475196B2
公开(公告)日：2009-01-06
申请号：US11388001
申请日：2006-03-23
IPC分类号： G06F13/00
CPC分类号： G06F12/0822 , G06F12/084
摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
摘要翻译： 数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。 响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓冲存储器确定目标存储器块相对于高速缓存存储器的一致性状态。 响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。 响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域 第二一致性状态。 然后，高速缓冲存储器播放具有所选范围的初始化请求。 响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。
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6.发明申请DATA PROCESSING SYSTEM, METHOD AND INTERCONNECT FABRIC SUPPORTING MULTIPLE PLANES OF PROCESSING NODES 审中-公开数据处理系统，方法和互连织物支持多个加工点的平面公开(公告)号：US20080225863A1
公开(公告)日：2008-09-18
申请号：US12124639
申请日：2008-05-21
IPC分类号： H04L12/56
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。
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7.发明授权Method and apparatus for handling multiple memory requests within a multiprocessor system 有权用于在多处理器系统内处理多个存储器请求的方法和装置公开(公告)号：US08214603B2
公开(公告)日：2012-07-03
申请号：US12024181
申请日：2008-02-01
CPC分类号： G06F9/526
摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.
摘要翻译： 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。 然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。
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公开(公告)号：US08140771B2
公开(公告)日：2012-03-20
申请号：US12024424
申请日：2008-02-01
CPC分类号： G06F12/0822
摘要： In at least one embodiment, a method of data processing in a data processing system having a memory hierarchy includes a processor core executing a storage-modifying memory access instruction to determine a memory address. The processor core transmits to a cache memory within the memory hierarchy a storage-modifying memory access request including the memory address, an indication of a memory access type, and, if present, a partial cache line hint signaling access to less than all granules of a target cache line of data associated with the memory address. In response to the storage-modifying memory access request, the cache memory performs a storage-modifying access to all granules of the target cache line of data if the partial cache line hint is not present and performs a storage-modifying access to less than all granules of the target cache line of data if the partial cache line hint is present.
摘要翻译： 在至少一个实施例中，具有存储器层次的数据处理系统中的数据处理方法包括执行存储修改存储器访问指令以确定存储器地址的处理器核心。 处理器核心向存储器层级内的高速缓冲存储器传送存储修改存储器访问请求，该存储修改存储器访问请求包括存储器地址，存储器访问类型的指示，以及如果存在的话，部分高速缓存行提示信令访问少于所有颗粒的 与存储器地址相关联的数据的目标高速缓存行。 响应于存储修改存储器访问请求，如果不存在部分高速缓存行提示，则高速缓存存储器对目标高速缓存行数据行的所有颗粒进行存储修改访问，并执行对小于全部的存储修改访问 如果存在部分高速缓存线提示，则目标高速缓存行数据的颗粒。
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9.发明授权Data processing system, method and interconnect fabric supporting multiple planes of processing nodes 有权支持多个处理节点平面的数据处理系统，方法和互连结构公开(公告)号：US07818388B2
公开(公告)日：2010-10-19
申请号：US11245887
申请日：2005-10-07
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A data processing system includes a first plane including a first plurality of processing nodes, each including multiple processing units, and a second plane including a second plurality of processing nodes, each including multiple processing units. The data processing system also includes a plurality of point-to-point first tier links. Each of the first plurality and second plurality of processing nodes includes one or more first tier links among the plurality of first tier links, where the first tier link(s) within each processing node connect a pair of processing units in the same processing node for communication. The data processing system further includes a plurality of point-to-point second tier links. At least a first of the plurality of second tier links connects processing units in different ones of the first plurality of processing nodes, at least a second of the plurality of second tier links connects processing units in different ones of the second plurality of processing nodes, and at least a third of the plurality of second tier links connects a processing unit in the first plane to a processing unit in the second plane.
摘要翻译： 数据处理系统包括包括第一多个处理节点的第一平面，每个处理节点包括多个处理单元，以及包括第二多个处理节点的第二平面，每个处理节点包括多个处理单元。 数据处理系统还包括多个点对点第一层链路。 第一多个处理节点和第二多个处理节点中的每一个包括多个第一层链路之中的一个或多个第一层链路，其中每个处理节点内的第一层链路连接相同处理节点中的一对处理单元，用于 通讯。 数据处理系统还包括多个点到点第二层链路。 所述多个第二层链路中的至少第一层连接所述第一多个处理节点中的不同处理节点中的处理单元，所述多个第二层链路中的至少一个链接连接所述第二多个处理节点中的不同处理节点中的处理单元， 并且所述多个第二层链路中的至少三分之一链路将所述第一平面中的处理单元连接到所述第二平面中的处理单元。
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公开(公告)号：US20090198971A1
公开(公告)日：2009-08-06
申请号：US12024220
申请日：2008-02-01
申请人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
发明人： Lakshminarayana B. Arimilli , Ravi K. Arimilli , Guy L. Guthrie , Charles F. Marino , William J. Starke
IPC分类号： G06F9/30
CPC分类号： G06F13/12
摘要： A heterogeneous processing element model is provided where I/O devices look and act like processors. In order to be treated like a processor, an I/O processing element, or other special purpose processing element, must follow some rules and have some characteristics of a processor, such as address translation, security, interrupt handling, and exception processing, for example. The heterogeneous processing element model puts special purpose processing elements on the same playing field as processors, from a programming perspective, operating system perspective, power perspective, as the processors. The operating system can get work to a security engine, for example, in the same way it does to a processor.
摘要翻译： 提供异构处理元件模型，其中I / O设备看起来像处理器一样操作。 为了像处理器一样处理I / O处理元件或其他专用处理元件，必须遵循一些规则并具有处理器的某些特性，例如地址转换，安全性，中断处理和异常处理，用于 例。 异构处理元素模型将特殊处理元素放在与处理器相同的竞争环境中，从编程角度，操作系统的角度，功率视角，作为处理器。 操作系统可以使用安全引擎，例如，与处理器相同。
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