公开(公告)号：US07454580B2

公开(公告)日：2008-11-18

申请号：US11380020

申请日：2006-04-25

申请人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

发明人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Robert A. Cargnoni ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F9/3842 ,  G06F9/3851 ,  G06F9/544

摘要： A data processing system includes a processor core and a memory subsystem. The memory subsystem includes a store queue having a plurality of entries, where each entry includes an address field for holding the target address of store operation, a data field for holding data for the store operation, and a virtual sync field indicating a presence or absence of a synchronizing operation associated with the entry. The memory subsystem further includes a store queue controller that, responsive to receipt at the memory subsystem of a sequence of operations including a synchronizing operation and a particular store operation, places a target address and data of the particular store operation within the address field and data field, respectively, of an entry in the store queue and sets the virtual sync field of the entry to represent the synchronizing operation, such that a number of store queue entries utilized is reduced.

摘要翻译： 数据处理系统包括处理器核心和存储器子系统。 存储器子系统包括具有多个条目的存储队列，其中每个条目包括用于保存存储操作的目标地址的地址字段，用于保存用于存储操作的数据的数据字段和指示存在或不存在的虚拟同步字段 与该条目相关联的同步操作。 存储器子系统还包括存储队列控制器，其响应于在存储器子系统处的接收包括同步操作和特定存储操作的一系列操作，将特定存储操作的目标地址和数据放置在地址字段和数据中 字段，并且设置条目的虚拟同步字段以表示同步操作，使得减少使用的存储队列条目的数量。

公开(公告)号：US07610458B2

公开(公告)日：2009-10-27

申请号：US11380018

申请日：2006-04-25

申请人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

发明人： Ravi K. Arimilli ,  Thomas M. Capasso ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F13/1631 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0846 ,  G06F12/0888

摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.

摘要翻译： 数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。 数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。 访问内存子系统的存储操作与第一个设置或第二个设置相关联。 数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成 在同步操作之后的存储操作之前。

公开(公告)号：US20080201533A1

公开(公告)日：2008-08-21

申请号：US12114790

申请日：2008-05-04

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。 输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。 失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。 调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。 通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

公开(公告)号：US07386682B2

公开(公告)日：2008-06-10

申请号：US11056764

申请日：2005-02-11

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。 输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。 失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。 调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。 通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

公开(公告)号：US07523268B2

公开(公告)日：2009-04-21

申请号：US12114790

申请日：2008-05-04

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. An incoming snoop request is entered in the first available latch in a pipeline of latches in a stall/reorder unit if the stall/reorder unit is not full. The entered snoop request is dispatched to a selector upon entering a bottom latch in the pipeline. The stall/reorder unit is not informed as to whether the dispatched snoop request is accepted by an arbitration mechanism for several clock cycles after the dispatch occurred. A copy of the dispatched snoop request is stored in a top latch in an overrun pipeline of latches in the first unit upon dispatching the snoop request. By maintaining information about the snoop request, the snoop request may be dispatched again to the selector in case the dispatched snoop request was rejected thereby increasing the chance that the snoop request will ultimately be accepted.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 如果失速/重新排序单元未满，则在失速/重新排序单元中的锁存器管线中的第一可用锁存器中输入进入的窥探请求。 输入的窥探请求在进入管道中的底部闩锁时被调度到选择器。 失速/重新排序单元不知道发送后发送的几个时钟周期是否由仲裁机制接受发送的窥探请求。 调度窥探请求的副本在调度窥探请求时被存储在第一单元中的锁存器的溢出管道中的顶部锁存器中。 通过维护关于窥探请求的信息，可以在被发送的窥探请求被拒绝的情况下再次发送到选择器的窥探请求，从而增加窥探请求将最终被接受的机会。

公开(公告)号：US08117390B2

公开(公告)日：2012-02-14

申请号：US12424434

申请日：2009-04-15

申请人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F13/00

CPC分类号： G06F12/0822 ,  G06F12/0897 ,  G06F2212/507

摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.

摘要翻译： 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送至至少一个上级高速缓冲存储器来服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。

公开(公告)号：US20080201534A1

公开(公告)日：2008-08-21

申请号：US12114786

申请日：2008-05-04

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/08

CPC分类号： G06F13/1605 ,  G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。

公开(公告)号：US07386681B2

公开(公告)日：2008-06-10

申请号：US11056679

申请日：2005-02-11

申请人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F13/1605 ,  G06F12/0831

摘要： A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. The snoop request is entered in the first available latch of the stall/reorder unit unless the stall/reorder unit is full in which case the new snoop request is transmitted to a second unit configured to transmit a request to retry resending the new snoop request. Snoop requests have a higher priority than requests from processors and snoop requests are selected by the arbitration mechanism over processor requests unless the arbitration mechanism requests otherwise (“stall request”) to the stall/reorder unit. By snoop requests having a higher priority than processor requests, the number of snoop requests rejected is reduced. By having the arbitration mechanism issue a stall request, the processor will not be starved.

摘要翻译： 用于减少拒绝的窥探请求数量的缓存，系统和方法。 缓存中的“停止/重新排序单元”从互连中接收窥探请求。 监听请求被输入到停止/重新排序单元的第一可用锁存器中，除非停止/重新排序单元已满，在这种情况下，新的窥探请求被发送到被配置为发送重新发送新的窥探请求的请求的第二单元。 侦听请求具有比来自处理器的请求更高的优先级，并且仲裁机制通过处理器请求选择侦听请求，除非仲裁机制另请求（“停止请求”）到停止/重新排序单元。 通过具有比处理器请求更高优先级的侦听请求，减少了被拒绝的侦听请求的数量。 通过使仲裁机制发出停顿请求，处理器不会饿死。

公开(公告)号：US20070288694A1

公开(公告)日：2007-12-13

申请号：US11423717

申请日：2006-06-13

申请人： Sanjeev Ghai ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

发明人： Sanjeev Ghai ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/3824 ,  G06F9/3834

摘要： A data processing system includes a processor core and a memory subsystem coupled to the processor core. The memory subsystem includes data storage and a store queue including a plurality of entries for buffering store operations to be performed with reference to the data storage. The memory subsystem further includes a store queue controller that gathers multiple store requests received from the processor core into a single store operation buffered within an entry of the store queue. The store queue controller applies store gathering windows of differing durations to differing ones of the plurality of entries in response to control information received from the processor core.

摘要翻译： 数据处理系统包括处理器核心和耦合到处理器核心的存储器子系统。 存储器子系统包括数据存储器和存储队列，其包括用于缓冲要参考数据存储器执行的存储操作的多个条目。 存储器子系统还包括存储队列控制器，其将从处理器核心接收的多个存储请求收集到缓冲在存储队列的条目内的单个存储操作中。 存储队列控制器响应于从处理器核心接收到的控制信息，将具有不同持续时间的商店收集窗口应用到多个条目中的不同条目。

公开(公告)号：US20100268884A1

公开(公告)日：2010-10-21

申请号：US12424434

申请日：2009-04-15

申请人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

发明人： David W. Cummings ,  Guy L. Guthrie ,  Hugh Shen ,  William J. Starke ,  Derek E. Williams ,  Phillip G. Williams

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0822 ,  G06F12/0897 ,  G06F2212/507

摘要： A processing unit for a data processing system includes a processor core having one or more execution units for processing instructions and a register file for storing data accessed in processing of the instructions. The processing unit also includes a multi-level cache hierarchy coupled to and supporting the processor core. The multi-level cache hierarchy includes at least one upper level of cache memory having a lower access latency and at least one lower level of cache memory having a higher access latency. The lower level of cache memory, responsive to receipt of a memory access request that hits only a partial cache line in the lower level cache memory, sources the partial cache line to the at least one upper level cache memory to service the memory access request. The at least one upper level cache memory services the memory access request without caching the partial cache line.

摘要翻译： 用于数据处理系统的处理单元包括具有一个或多个用于处理指令的执行单元的处理器核心和用于存储在指令处理中访问的数据的寄存器文件。 处理单元还包括耦合到并支持处理器核的多级高速缓存层级。 多级高速缓存层级包括具有较低访问延迟的至少一个高级缓存存储器和具有较高访问延迟的至少一个较低级别的高速缓存存储器。 响应于仅接收低级高速缓冲存储器中的部分高速缓存行的存储器访问请求的响应，较低级别的高速缓存存储器将部分高速缓存行源送到至少一个上级高速缓冲存储器以服务存储器访问请求。 至少一个上级缓存存储器服务于存储器访问请求，而不缓存部分高速缓存行。