公开(公告)号：US07193500B2

公开(公告)日：2007-03-20

申请号：US10711460

申请日：2004-09-20

申请人： Anil K. Chinthakindi ,  Anita Madan ,  Kenneth J. Stein ,  Kwong Hon Wong

发明人： Anil K. Chinthakindi ,  Anita Madan ,  Kenneth J. Stein ,  Kwong Hon Wong

IPC分类号： H01C1/012

CPC分类号： H01C17/075 ,  H01C7/006 ,  H01C7/06

摘要： An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.

摘要翻译： 集成电路包括双层薄膜电阻器，其中下层是控制上层晶体结构的晶种层。 可以选择下层的厚度和上层的厚度以形成具有设计值的TCR的电阻器。

公开(公告)号：US07622386B2

公开(公告)日：2009-11-24

申请号：US11567517

申请日：2006-12-06

申请人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

发明人： Anita Madan ,  Robert J. Purtell ,  Keith Kwong Hon Wong ,  Jun-Keun Kwak

IPC分类号： H01L21/44

CPC分类号： H01L21/28518

摘要： A method of forming silicide contacts for semiconductor devices includes subjecting a silicon containing semiconductor wafer to a degas treatment at an initial degas temperature of about 250 to about 400° C., transferring the semiconductor wafer from a degas chamber to a deposition chamber, depositing a nickel containing layer over the wafer following transfer of the wafer from the degas chamber to the deposition chamber, and annealing the semiconductor wafer so as to create silicide regions at portions on the wafer where nickel material is formed over silicon.

摘要翻译： 形成用于半导体器件的硅化物触点的方法包括在约250至约400℃的初始脱气温度下对含硅半导体晶片进行脱气处理，将半导体晶片从脱气室转移至沉积室， 将晶片从脱气室转移到沉积室之后，在晶片上方的镍含量层，以及对半导体晶片进行退火，以在晶片上形成硅材料的部分上形成硅化物区域，其中镍材料形成在硅上。

公开(公告)号：US20080045039A1

公开(公告)日：2008-02-21

申请号：US11873721

申请日：2007-10-17

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

公开(公告)号：US20080036007A1

公开(公告)日：2008-02-14

申请号：US11875217

申请日：2007-10-19

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20070007548A1

公开(公告)日：2007-01-11

申请号：US11160705

申请日：2005-07-06

申请人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

发明人： Richard Conti ,  Ronald Bourque ,  Nancy Klymko ,  Anita Madan ,  Michael Smits ,  Roy Tilghman ,  Kwong Wong ,  Daewon Yang

IPC分类号： H01L21/8234 ,  H01L27/10 ,  H01L21/31

CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。

公开(公告)号：US20100208869A1

公开(公告)日：2010-08-19

申请号：US12372104

申请日：2009-02-17

申请人： Thomas N. Adam ,  Eric C. Harley ,  Anita Madan ,  Teresa L. Pinto

发明人： Thomas N. Adam ,  Eric C. Harley ,  Anita Madan ,  Teresa L. Pinto

IPC分类号： G01N23/20 ,  G06F17/00

CPC分类号： G01N23/20 ,  G01N2223/6116

摘要： In a method for use of x-ray diffraction to measure the strain on the top silicon germanium layer of an SOI substrate, the location of the peak diffraction area of an upper silicon layer of the SOI substrate is determined by first determining the peak diffraction area of the upper silicon layer on a reference pad (where the SOI thickness is about 700-900 Angstroms) within a die formed on a semiconductor wafer. The x-ray beam then moves to that location on the pad of interest to be measured and begins the XRD scan on the pad of interest to ultimately determine the strain of the top silicon germanium layer of the pad of interest

摘要翻译： 在使用x射线衍射测量SOI衬底的顶部硅锗层上的应变的方法中，SOI衬底的上硅层的峰值衍射面积的位置是通过首先确定峰值衍射面积 在半导体晶片上形成的晶片内的参考焊盘（其中SOI厚度为约700-900埃）上硅层。 X射线束然后移动到要测量的感兴趣的焊盘上的该位置，并且在感兴趣的焊盘上开始XRD扫描，以最终确定感兴趣焊盘顶部硅锗层的应变

公开(公告)号：US07119016B2

公开(公告)日：2006-10-10

申请号：US10684596

申请日：2003-10-15

申请人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

发明人： Ashima B. Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Wayne Dibello ,  Ramaseshan Suryanarayanan Iyer

IPC分类号： H01L21/36

CPC分类号： C23C16/36 ,  C23C16/24 ,  H01L21/02532 ,  H01L21/0262

摘要： A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

摘要翻译： 至少包含任何组合中的Si，N和C的化合物，例如式（R-NH）4-n-SiX n N的化合物，其中R是烷基 （其可以相同或不同），n为1,2或3，X为H或卤素（例如双叔丁基氨基硅烷（BTBAS））可与硅烷或硅烷衍生物混合 制作一部电影。 可以通过混合硅烷（SiH 4 SO 4）或硅烷衍生物和包括Si，N和C的化合物如BTBAS来生长多晶硅硅膜。 可以通过改变试剂和条件来生长可控地掺杂有碳和/或氮的膜（例如层状膜）。

公开(公告)号：US08105955B2

公开(公告)日：2012-01-31

申请号：US11464664

申请日：2006-08-15

申请人： Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

发明人： Jin Ping Liu ,  Richard J. Murphy ,  Anita Madan ,  Ashima B. Chakravarti

IPC分类号： H01L21/31

CPC分类号： H01L29/78 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532 ,  H01L29/1054

摘要： An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.

摘要翻译： 集成电路系统包括衬底，衬底上的含碳的硅区域，衬底上的非含碳的硅区域和包含非含碳硅区域和碳 - 碳区域的硅 - 碳区域， 含硅区域。

公开(公告)号：US20060087400A1

公开(公告)日：2006-04-27

申请号：US10711460

申请日：2004-09-20

申请人： Anil Chinthakindi ,  Anita Madan ,  Kenneth Stein ,  Kwong Wong

发明人： Anil Chinthakindi ,  Anita Madan ,  Kenneth Stein ,  Kwong Wong

IPC分类号： H01C1/012

CPC分类号： H01C17/075 ,  H01C7/006 ,  H01C7/06

摘要： An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.

摘要翻译： 集成电路包括双层薄膜电阻器，其中下层是控制上层晶体结构的晶种层。 可以选择下层的厚度和上层的厚度以形成具有设计值的TCR的电阻器。

公开(公告)号：US20050085054A1

公开(公告)日：2005-04-21

申请号：US10684596

申请日：2003-10-15

申请人： Ashima Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Dibello ,  Ramaseshan Iyer

发明人： Ashima Chakravarti ,  Anita Madan ,  Woo-Hyeong Lee ,  Gregory Dibello ,  Ramaseshan Iyer

IPC分类号： C23C16/24 ,  C23C16/36 ,  C30B1/00 ,  H01L21/20 ,  H01L21/205 ,  H01L21/36

CPC分类号： C23C16/36 ,  C23C16/24 ,  H01L21/02532 ,  H01L21/0262

摘要： A compound that includes at least Si, N and C in any combination, such as compounds of formula (R—NH)4-nSiXn wherein R is an alkyl group (which may be the same or different), n is 1, 2 or 3, and X is H or halogen (such as, e.g., bis-tertiary butyl amino silane (BTBAS)), may be mixed with silane or a silane derivative to produce a film. A polysilicon silicon film may be grown by mixing silane (SiH4) or a silane derviative and a compound including Si, N and C, such as BTBAS. Films controllably doped with carbon and/or nitrogen (such as layered films) may be grown by varying the reagents and conditions.

摘要翻译： 至少包含任何组合中的Si，N和C的化合物，例如式（R-NH）4-n-SiX n N的化合物，其中R是烷基 （其可以相同或不同），n为1,2或3，X为H或卤素（例如双叔丁基氨基硅烷（BTBAS））可与硅烷或硅烷衍生物混合 制作一部电影。 可以通过混合硅烷（SiH 4 SO 4）或硅烷衍生物和包括Si，N和C的化合物如BTBAS来生长多晶硅硅膜。 可以通过改变试剂和条件来生长可控地掺杂有碳和/或氮的膜（例如层状膜）。