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公开(公告)号：US07193500B2
公开(公告)日：2007-03-20
申请号：US10711460
申请日：2004-09-20
IPC分类号： H01C1/012
CPC分类号： H01C17/075 , H01C7/006 , H01C7/06
摘要： An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.
摘要翻译： 集成电路包括双层薄膜电阻器，其中下层是控制上层晶体结构的晶种层。 可以选择下层的厚度和上层的厚度以形成具有设计值的TCR的电阻器。
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公开(公告)号：US06696343B1
公开(公告)日：2004-02-24
申请号：US10459978
申请日：2003-06-12
申请人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
发明人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
IPC分类号： H01L2120
CPC分类号： H01G5/18 , B81B2201/01 , H01G5/011 , Y10S257/924
摘要： A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.
摘要翻译： 描述了三维微机电（MEM）变容二极管，其中可移动光束和固定电极分别制造在彼此耦合的分开的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。
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公开(公告)号：US06661069B1
公开(公告)日：2003-12-09
申请号：US10278211
申请日：2002-10-22
申请人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
发明人： Anil K. Chinthakindi , Robert A. Groves , Kenneth J. Stein , Seshadri Subbanna , Richard P. Volant
IPC分类号： H01L2986
CPC分类号： H01G5/18 , B81B2201/01 , H01G5/011 , Y10S257/924
摘要： A three-dimensional micro- electromechanical (MEM) varactor is described wherein a movable beam and fixed electrode are respectively fabricated on separate substrates coupled to each other. The movable beam with comb-drive electrodes are fabricated on the “chip side” while the fixed bottom electrode is fabricated on a separated substrate “carrier side”. Upon fabrication of the device on both surfaces of the substrate, the chip side device is diced and “flipped over”, aligned and joined to the “carrier” substrate to form the final device. Comb-drive (fins) electrodes are used for actuation while the motion of the electrode provides changes in capacitance. Due to the constant driving forces involved, a large capacitance tuning range can be obtained. The three dimensional aspect of the device avails large surface area. When large aspect ratio features are provided, a lower actuation voltage can be used. Upon fabrication, the MEMS device is completely encapsulated, requiring no additional packaging of the device. Further, since alignment and bonding can be done on a wafer scale (wafer scale MEMS packaging), an improved device yield can be obtained at a lower cost.
摘要翻译： 描述了三维微机电（MEM）变容二极管，其中可移动光束和固定电极分别制造在彼此耦合的分开的基板上。 具有梳状驱动电极的可移动光束在“芯片侧”上制造，而固定底部电极制造在分离的基板“载体侧”上。 在衬底的两个表面上制造器件时，芯片侧器件被切割并“翻转”，对准并接合到“载体”衬底以形成最终器件。 梳状驱动（鳍）电极用于致动，同时电极的运动提供电容的变化。 由于所涉及的驱动力恒定，可以获得大的电容调谐范围。 该装置的三维方面具有较大的表面积。 当提供大的纵横比特征时，可以使用较低的致动电压。 在制造时，MEMS器件被完全封装，不需要额外的器件封装。 此外，由于可以在晶片规模（晶片级MEMS封装）上进行取向和接合，所以可以以更低的成本获得改进的器件产量。
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公开(公告)号：US07012499B2
公开(公告)日：2006-03-14
申请号：US10250075
申请日：2003-06-02
IPC分类号： H01C7/06
摘要： A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).
摘要翻译： 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。
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公开(公告)号：US06890810B2
公开(公告)日：2005-05-10
申请号：US10727946
申请日：2003-12-04
IPC分类号： H01C7/00 , H01C7/06 , H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
摘要： A thin film resistor that has a substantially zero TCR is provided as well as a method for fabricating the same. The thin film resistor includes at least two resistor materials located over one another. Each resistor material has a different temperature coefficient of resistivity such that the effective temperature coefficient of resistivity of the thin film resistor is substantially 0 ppm/° C. The thin film resistor may be integrated into a interconnect structure or it may be integrated with a metal-insulator-metal capacitor (MIMCAP).
摘要翻译： 提供具有基本为零TCR的薄膜电阻器及其制造方法。 薄膜电阻器包括彼此位于的至少两个电阻材料。 每个电阻器材料具有不同的电阻率温度系数，使得薄膜电阻器的电阻率的有效温度系数基本上为0ppm /℃。薄膜电阻器可以集成到互连结构中，或者可以与金属 - 绝缘体 - 金属电容器（MIMCAP）。
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公开(公告)号：US07022246B2
公开(公告)日：2006-04-04
申请号：US10336992
申请日：2003-01-06
申请人： Anil K. Chinthakindi , Shwu-Jen Jeng , Michael F. Lofaro , Christopher M. Schnabel , Kenneth J. Stein
发明人： Anil K. Chinthakindi , Shwu-Jen Jeng , Michael F. Lofaro , Christopher M. Schnabel , Kenneth J. Stein
IPC分类号： H01L21/302
CPC分类号： H01L28/20 , H01L23/5223 , H01L27/0802 , H01L27/0805 , H01L28/40 , H01L2924/0002 , Y10S438/97 , Y10T29/49082 , Y10T29/49155 , H01L2924/00
摘要： A method is disclosed of fabricating a MIMCAP (a capacitor (CAP) formed by successive layers of metal, insulator, metal (MIM)) and a thin film resistor at the same level. A method is also disclosed of fabricating a MIMCAP and a thin film resistor at the same level, and a novel integration scheme for BEOL (back-end-of-line processing) thin film resistors which positions them closer to FEOL (front-end-of-line processing) devices.
摘要翻译： 公开了制造MIMCAP（由金属，绝缘体，金属（MIM）的连续层形成的电容器（CAP））和同一水平的薄膜电阻器的方法。 还公开了制造相同水平的MIMCAP和薄膜电阻器的方法，以及用于BEOL（后端处理）薄膜电阻器的新颖的集成方案，使它们更接近FEOL（前端 - 线上处理）设备。
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公开(公告)号：US07643268B2
公开(公告)日：2010-01-05
申请号：US12194566
申请日：2008-08-20
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01G4/228 , H01L27/108 , H01L29/94
CPC分类号： H01G4/228 , H01G4/30 , H01G4/33 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10T29/417 , Y10T29/435 , H01L2924/00
摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.
摘要翻译： 公开了具有数字化的垂直板的电容器的实施例以及形成电容器的方法，使得板之间的有效间隙距离减小。 该间隙宽度减小显着增加了电容器的电容密度。 通过用节点掩蔽连接点，通过从垂直板之间蚀刻电介质材料，并通过从垂直板下方蚀刻牺牲材料，在线加工的后端完成间隙宽度减小。 一旦牺牲材料被去除，介质材料之间的介电材料的蚀刻形成气隙，并且可以使用各种技术来使板在这些气隙上塌陷。 可以通过沉积第二电介质材料（例如，高k电介质）来填充任何剩余的气隙，这将进一步增加电容密度并封装电容器，以使得垂直板之间的距离减小。
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公开(公告)号：US07608909B2
公开(公告)日：2009-10-27
申请号：US11164765
申请日：2005-12-05
IPC分类号： H01L21/76
CPC分类号： H01P11/003 , H01L21/7682 , H01L21/76838 , H01L23/5222 , H01L23/5225 , H01L23/53238 , H01L2223/6622 , H01L2223/6627 , H01L2924/0002 , H01L2924/1903 , H01L2924/3011 , H01L2924/00
摘要： A method for forming a transmission line structure for a semiconductor device includes forming an interlevel dielectric layer over a first metallization level, removing a portion of the interlevel dielectric layer and forming a sacrificial material within one or more voids created by the removal of the portion of the interlevel dielectric layer. A signal transmission line is formed in a second metallization level formed over the interlevel dielectric layer, the signal transmission line being disposed over the sacrificial material. A portion of dielectric material included within the second metallization level is removed so as to expose the sacrificial material, wherein a portion of the sacrificial material is exposed through a plurality of access holes formed through the signal transmission line. The sacrificial material is removed so as to create an air gap beneath the signal transmission line.
摘要翻译： 用于形成用于半导体器件的传输线结构的方法包括在第一金属化层上形成层间电介质层，去除层间电介质层的一部分，并在通过去除部分的部分产生的一个或多个空隙内形成牺牲材料 层间电介质层。 信号传输线形成在层间电介质层上形成的第二金属化层，信号传输线设置在牺牲材料之上。 包括在第二金属化水平内的电介质材料的一部分被去除以暴露牺牲材料，其中牺牲材料的一部分通过穿过信号传输线形成的多个访问孔而露出。 去除牺牲材料，以在信号传输线下方产生气隙。
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公开(公告)号：US20090032904A1
公开(公告)日：2009-02-05
申请号：US11831208
申请日：2007-07-31
CPC分类号： H01L27/0805 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A plurality of interdigitized conductive fingers are arranged to form a substantially square configuration in each of a plurality of layers separated by a high dielectric constant material, wherein each of the plurality of interdigitized conductive fingers includes at least one bend of substantially ninety degrees. The plurality of interdigitized conductive fingers includes a first set of fingers that are connected to an anode terminal, and a second set of fingers that are connected to a cathode terminal. The plurality of layers includes a bottommost layer that is in closest proximity to a substrate relative to other layers of the plurality of layers. The bottommost layer does not include any fingers connected to the anode terminal.
摘要翻译： 多个交叉指状的导电指状物被布置成在由高介电常数材料分离的多个层中的每一层中形成基本上正方形的构造，其中多个交叉指状导电指状物中的每一个包括至少一个基本上90度的弯曲部。 多个交叉指状的导电指状物包括连接到阳极端子的第一组指状物和连接到阴极端子的第二组指状物。 多个层包括相对于多个层中的其它层最靠近衬底的最底层。 最底层不包括连接到阳极端子的任何手指。
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公开(公告)号：US20080305606A1
公开(公告)日：2008-12-11
申请号：US12194564
申请日：2008-08-20
申请人： Anil K. Chinthakindi
发明人： Anil K. Chinthakindi
IPC分类号： H01L21/20
CPC分类号： H01G4/228 , H01G4/30 , H01G4/33 , H01L23/5223 , H01L28/60 , H01L2924/0002 , Y10T29/417 , Y10T29/435 , H01L2924/00
摘要： Disclosed are embodiments of a capacitor with inter-digitated vertical plates and a method of forming the capacitor such that the effective gap distance between plates is reduced. This gap width reduction significantly increases the capacitance density of the capacitor. Gap width reduction is accomplished during back end of the line processing by masking connecting points with nodes, by etching the dielectric material from between the vertical plates and by etching a sacrificial material from below the vertical plates. Etching of the dielectric material from between the plates forms air gaps and various techniques can be used to cause the plates to collapse in on these air gaps, once the sacrificial material is removed. Any remaining air gaps can be filled by depositing a second dielectric material (e.g., a high k dielectric), which will further increase the capacitance density and will encapsulate the capacitor in order to make the reduced distance between the vertical plates permanent.
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