-
11.发明授权High-density erasable programmable logic device architecture using multiplexer interconnections 失效使用多路复用器互连的高密度可擦除可编程逻辑器件架构
公开(公告)号：US5268598A
公开(公告)日：1993-12-07
申请号：US043146
申请日：1993-03-31
申请人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
发明人： Bruce B. Pedersen , David Chiang , Francis B. Heile , Cameron McClintock , Hock-Chuen So , James A. Watson
IPC分类号： H03K19/173 , H03K19/177 , H03R19/177
CPC分类号： H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17764 , H03K19/17784 , H03K19/17792
摘要： A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to logic array blocks. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes the user's ability to route a selected line to the output of a selected multiplexer, while at the same time maintaining higher speed and lower power consumption, and using less chip array than prior art programmable logic devices using programmable interconnect arrays based on erasable programmable read-only memories.
摘要翻译： 提出了一种可编程逻辑器件，其包括全局互连阵列，其线路经由可编程多路复用器馈送到逻辑阵列块。 全局互连阵列线以特定模式馈送到多路复用器，其最大化用户将所选线路路由到所选择的多路复用器的输出的能力，同时保持更高的速度和更低的功耗，并且使用更少的芯片阵列 比使用基于可擦除可编程只读存储器的可编程互连阵列的现有技术的可编程逻辑器件。
-
公开(公告)号：US5847617A
公开(公告)日：1998-12-08
申请号：US909337
申请日：1997-08-11
CPC分类号： H03L7/0997 , H03K3/0315
摘要： A variable-path-length voltage-controlled oscillator circuit is provided. The oscillator circuit has a ring oscillator formed from a series of voltage-controlled inverter stages. The path length (i.e., the number of inverter stages) in the ring is selected based on path length configuration data stored in memory. The selected path length determines the nominal or center frequency of operation of the ring oscillator. The output frequency of the oscillator circuit is voltage-tuned about this center frequency by varying the delay of each inverter stage in the ring oscillator path. Various types of voltage-controlled inverter stages may be used, including current-starved inverter stages, variable-capacitive-load inverter stages, and differential-delay inverter stages. The voltage-controlled oscillator circuit may be used in a phase-locked loop on a programmable logic device for frequency synthesis or to eliminate clock skew.
摘要翻译： 提供了可变路径长度的压控振荡器电路。 振荡器电路具有由一系列压控逆变器级形成的环形振荡器。 基于存储在存储器中的路径长度配置数据来选择环路的路径长度（即，逆变器级数）。 所选择的路径长度决定了环形振荡器的额定或中心频率。 通过改变环形振荡器路径中每个反相器级的延迟，振荡器电路的输出频率就关于该中心频率进行电压调谐。 可以使用各种类型的压控变频器级，包括电流欠压级，可变容性负载逆变级和差分延迟逆变级。 压控振荡器电路可用于可编程逻辑器件上的锁相环，用于频率合成或消除时钟偏移。
-
公开(公告)号：US06836151B1
公开(公告)日：2004-12-28
申请号：US10781334
申请日：2004-02-17
IPC分类号： H03K190195
CPC分类号： H03K19/018585
摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。
-
公开(公告)号：US06714050B2
公开(公告)日：2004-03-30
申请号：US09898183
申请日：2001-07-03
IPC分类号： H03K190195
CPC分类号： H03K19/17744 , H03K19/018585
摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
-
公开(公告)号：US07034570B2
公开(公告)日：2006-04-25
申请号：US11004664
申请日：2004-12-03
IPC分类号： H03K19/177
CPC分类号： H03K19/018585
摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
摘要翻译： 提供电路以单独配置集成电路的每个I / O以与不同的LVTTL I / O标准兼容。 这可以通过仅一个I / O电源电压完成，其中该电压是特定应用中所需的I / O电压中最高的。 电路通过调节I / O单元的输出电压进行操作，使其高于VOH并低于其符合的LVTTL标准的最大VIH。 由于每个I / O单元都可单独配置，任何I / O都可以驱动到任何LVTTL规范。
-
公开(公告)号：US06271679B1
公开(公告)日：2001-08-07
申请号：US09535064
申请日：2000-03-23
IPC分类号： H03K19177
CPC分类号： H03K19/17744 , H03K19/018585
摘要： Circuitry is provided to individually configure each I/O of an integrated circuit to be compatible with a different LVTTL I/O standards. This can be done with only one I/O supply voltage, where that voltage is the highest of the I/O voltages needed in a particular application. The circuitry operates by regulating the output voltage of the I/O cell so that it is above the VOH and below the maximum VIH for the LVTTL standard for which it will comply with. Since each I/O cell is individually configurable, any I/O can drive out to any LVTTL specification.
-
公开(公告)号：US06661253B1
公开(公告)日：2003-12-09
申请号：US09931475
申请日：2001-08-16
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H03K19177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
-
公开(公告)号：US6034536A
公开(公告)日：2000-03-07
申请号：US982297
申请日：1997-12-01
IPC分类号： G06F11/20 , G11C29/00 , H03K19/177 , H03K19/003 , H03K19/173
CPC分类号： H03K19/17764 , G11C29/808 , H03K19/17728 , H03K19/17736
摘要： Redundant circuitry for a logic circuit such as a programmable logic device is provided. The redundant circuitry allows the logic circuit to be repaired by replacing a defective logic area on the circuit with a redundant logic circuit. Rows and columns of logic areas may be logically remapped by row and column swapping. The logic circuit contains dynamic control circuitry for directing programming data to various logic areas on the circuit in an order defined by redundancy configuration data. Redundancy may be implemented using either fully or partially redundant logic areas. Logic areas may be swapped to remap a partially redundant logic area onto a logic area containing a defect. The defect may then be repaired using row or column swapping or shifting. A logic circuit containing folded rows of logic areas may be repaired by replacing a defective half-row with a redundant half-row.
-
19.发明授权Programmable logic array device with grouped logic regions and three types of conductors 失效具有分组逻辑区和三种类型导体的可编程逻辑阵列器件
公开(公告)号：US5598109A
公开(公告)日：1997-01-28
申请号：US626513
申请日：1996-04-02
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17704 , H03K19/17744
摘要： A programmable logic array device in which programmable logic regions are arranged in groups of four is provided. The device includes direct connect conductors for carrying signals totally within one group of four regions as well as to certain adjacent programmable logic regions, local conductors for carrying signals within groups and among adjacent groups, and global conductors for carrying device-wide signals. Connections among the various conductors, and between conductors and programmable logic regions, are provided to optimize the connection resources by avoiding switched conductor paths wherever possible.
摘要翻译： 提供了可编程逻辑阵列器件，其中可编程逻辑区域以四个成组排列。 该装置包括用于在四个区域的一组内以及某些相邻的可编程逻辑区域中携带信号的直接连接导体，用于在组内和相邻组之间传送信号的本地导体以及用于承载设备范围信号的全局导体。 提供各种导体之间以及导体和可编程逻辑区之间的连接，以尽可能避免开关导体路径来优化连接资源。
-
公开(公告)号：US07800405B2
公开(公告)日：2010-09-21
申请号：US12484665
申请日：2009-06-15
申请人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
发明人： Andy L. Lee , Wanli Chang , Cameron McClintock , John E. Turner , Brian D. Johnson , Chiao Kai Hwang , Richard Yen-Hsiang Chang , Richard G. Cliff
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/063 , H03K19/177 , H03K19/1778
摘要： Enhanced passgate structures for use in low-voltage systems are presented in which the influence of Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the VGATE-Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
摘要翻译： 提出了用于低压系统的增强型门控结构，其中Vt对单晶闸管通道通过的信号范围的影响减小。 在一种布置中，通过应用较高的VGATE来提高通过NMOS通道传播的信号的VGATE-Vt极限; 在另一种布置中，Vt被降低。 传统上使用单通道闸门的CMOS传动闸门的使用也被提出。
-
-
-
-
-
-
-
-
-
搜索结果
62 条记录 (耗时 0.048 秒)