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    Flexible accumulator in digital signal processing circuitry
    2.
    发明授权
    Flexible accumulator in digital signal processing circuitry 失效
    灵活的累加器在数字信号处理电路中

    公开(公告)号：US07660841B2

    公开(公告)日：2010-02-09

    申请号：US10783789

    申请日：2004-02-20

    申请人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    发明人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    IPC分类号： G06F7/38

    CPC分类号： G06F7/5443 ,  G06F2207/3884

    摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.

    摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

    Data latch with low-power bypass mode
    3.
    发明授权
    Data latch with low-power bypass mode 失效
    低功耗旁路模式的数据锁存器

    公开(公告)号：US06958624B1

    公开(公告)日：2005-10-25

    申请号：US10437426

    申请日：2003-05-12

    申请人： Gregory Starr ,  Martin Langhammer ,  Chiao Kai Hwang

    发明人： Gregory Starr ,  Martin Langhammer ,  Chiao Kai Hwang

    IPC分类号： H03K3/012 ,  H03K3/037 ,  H03K19/177

    CPC分类号： H03K3/012 ,  H03K3/0372

    摘要： A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

    摘要翻译： 在旁路模式下，旁路锁存电路消耗的功率要小于锁存模式。 该电路包括一个触发器，其触发器的输出被路由到多路复用器的输入端。 多路复用器的另一个输入也是触发器的输入。 多路复用器用于选择锁存输出，即注册或锁存的触发器输出或触发器输入。 通过用触发器时钟输入替换逆变器来修改触发器，逻辑门接受作为时钟输入和控制输入的输入。 控制输入​​可以使触发器忽略时钟，从而防止通过在触发器中对电容元件充电和放电来消耗功率的开关。

    Programmable logic device including multipliers and configurations thereof to reduce resource utilization
    4.
    发明授权
    Programmable logic device including multipliers and configurations thereof to reduce resource utilization 有权
    可编程逻辑器件包括乘法器及其配置，以减少资源利用

    公开(公告)号：US06693455B2

    公开(公告)日：2004-02-17

    申请号：US10377962

    申请日：2003-02-26

    申请人： Martin Langhammer ,  Chiao Kai Hwang ,  Gregory Starr

    发明人： Martin Langhammer ,  Chiao Kai Hwang ,  Gregory Starr

    IPC分类号： H03K19177

    CPC分类号： H03K19/17744 ,  G06F7/523 ,  G06F2207/3816 ,  H03K19/17728 ,  H03K19/17732

    摘要： In a programmable logic device having dedicated multiplier circuitry, some of the scan chain registers normally used for testing the device are located adjacent input registers of the multipliers. Those scan chain registers are ANDed with the input registers, and can be loaded with templates of ones and zeroes. This allows, e.g., subset multiplication if the least significant bits are loaded with zeroes and the remaining bits are loaded with ones. The multipliers preferably are arranged in blocks with other components, such as adders, that allow them to be configured as finite impulse response (FIR) filters. In such configurations, the scan chain registers can be used to load filter coefficients, avoiding the use of scarce logic and routing resources of the device.

    摘要翻译： 在具有专用乘法器电路的可编程逻辑器件中，通常用于测试器件的扫描链寄存器中的一些位于乘法器的输入寄存器附近。 那些扫描链寄存器与输入寄存器进行“与”运算，可以加载一个和零个的模板。 这允许例如子集乘法，如果最低有效位被加载为零，并且其余位被加载为零。 乘法器优选地被布置成具有允许它们被配置为有限脉冲响应（FIR）滤波器的其他组件（例如加法器）的块。 在这种配置中，扫描链寄存器可用于加载滤波器系数，避免使用稀缺的逻辑和设备的路由资源。

    Flexible accumulator in digital signal processing circuitry
    5.
    发明授权
    Flexible accumulator in digital signal processing circuitry 有权
    灵活的累加器在数字信号处理电路中

    公开(公告)号：US09170775B2

    公开(公告)日：2015-10-27

    申请号：US12683686

    申请日：2010-01-07

    申请人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    发明人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    IPC分类号： G06F7/38 ,  G06F7/544

    CPC分类号： G06F7/5443 ,  G06F2207/3884

    摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.

    摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。

    Programmable logic device with specialized functional block
    6.
    发明授权
    Programmable logic device with specialized functional block 有权
    具有专门功能块的可编程逻辑器件

    公开(公告)号：US08364738B1

    公开(公告)日：2013-01-29

    申请号：US12715645

    申请日：2010-03-02

    申请人： Martin Langhammer ,  Leon Zheng ,  Chiao Kai Hwang ,  Gregory Starr

    发明人： Martin Langhammer ,  Leon Zheng ,  Chiao Kai Hwang ,  Gregory Starr

    IPC分类号： G06F7/00 ,  G06F15/00

    CPC分类号： G06F7/5324

    摘要： In a programmable logic device having a specialized functional block incorporating multipliers and adders, multiplication operations that do not fit neatly into the available multipliers are performed partially in the multipliers of the specialized functional block and partially in multipliers configured in programmable logic of the programmable logic device. Unused resources of the specialized functional block, including adders, may be used to add together the partial products produced inside and outside the specialized functional block. Some adders configured in programmable logic of the programmable logic device also may be used for that purpose.

    摘要翻译： 在具有包含乘法器和加法器的专用功能块的可编程逻辑器件中，不能完全适合于可用乘法器的乘法运算部分地在专用功能块的乘法器中部分地执行，并且部分地在可编程逻辑器件的可编程逻辑中配置的乘法器 。 专业功能块的未使用资源（包括加法器）可用于将专门功能块内部和外部生成的部分产品加在一起。 在可编程逻辑器件的可编程逻辑中配置的一些加法器也可以用于该目的。

    FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY
    7.
    发明申请
    FLEXIBLE ACCUMULATOR IN DIGITAL SIGNAL PROCESSING CIRCUITRY 审中-公开
    数字信号处理电路中的灵活累加器

    公开(公告)号：US20100169404A1

    公开(公告)日：2010-07-01

    申请号：US12683686

    申请日：2010-01-07

    申请人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    发明人： Leon Zheng ,  Martin Langhammer ,  Nitin Prasad ,  Greg Starr ,  Chiao Kai Hwang ,  Kumara Tharmalingam

    IPC分类号： G06F7/44 ,  G06F7/42

    CPC分类号： G06F7/5443 ,  G06F2207/3884

    摘要： A multiplier-accumulator (MAC) block can be programmed to operate in one or more modes. When the MAC block implements at least one multiply-and-accumulate operation, the accumulator value can be zeroed without introducing clock latency or initialized in one clock cycle. To zero the accumulator value, the most significant bits (MSBs) of data representing zero can be input to the MAC block and sent directly to the add-subtract-accumulate unit. Alternatively, dedicated configuration bits can be set to clear the contents of a pipeline register for input to the add-subtract-accumulate unit.

    摘要翻译： 乘法器累加器（MAC）块可以编程为在一个或多个模式下运行。 当MAC块实现至少一个乘法和累加操作时，累加器值可以归零，而不会引入时钟延迟或在一个时钟周期内初始化。 为了使累加器值为零，代表零的数据的最高有效位（MSB）可以输入到MAC块，并直接发送到加减法累加单元。 或者，可以设置专用配置位以清除流水线寄存器的内容，以输入到加法累加单元。