摘要:
The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.
摘要:
An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).
摘要:
The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.
摘要:
An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward bias a junction of the SCR. The external pumping circuit can comprise a transistor that can be coupled to a region of the SCR to pump the region.
摘要:
A structure is designed with an external terminal (100) and a reference terminal (102). A first transistor (106) is formed on a substrate. The first transistor has a current path coupled between the external terminal and the reference terminal. A second transistor (118) has a current path coupled between the external terminal and the substrate. A third transistor (120) has a current path coupled between the substrate and the reference terminal.
摘要:
Methods and circuits are disclosed for protecting an electronic circuit from ESD damage using an SCR ESD cell. An SCR circuit is coupled to a terminal of an associated microelectronic circuit for which ESD protection is desired. The SCR used in the ESD cell of the invention is provided with a full guardring for shielding the SCR from triggering by fast transients. A resistor is provided at the guardring for use in triggering the SCR at the onset of an ESD event. Exemplary preferred embodiments of the invention are disclosed with silicide-block resistors within the range of about 2-1000 Ohms or less.
摘要:
An equipment (400) for testing semiconductor device performance under high energy pulse conditions, which comprises a high voltage generator (401) and an on/off switch relay (403). The relay is resistively connected by a first resistor (402) to the generator and by a second resistor (404) to the socket (405a) for the device-under-test (406); the relay is operable in a partially ionized ambient. A capacitor (407) is connected to the relay, to the generator, and to the device, and is operable to discharge high energy pulses through the device. A third resistor (410) is in parallel with the capacitor and the device, and is operable to suppress spurious pulses generated by the relay. This third resistor has a value between about 1 kΩ and 1 MΩ, preferably about 10 kΩ, several orders of magnitude greater than the on-resistance of the device-under-test.
摘要:
A protection circuit is designed with an external terminal (300), a reference terminal (126) and a substrate (342). A semiconductor body (338) is formed by an isolation region (332, 340) formed between the substrate and the semiconductor body, thereby enclosing the semiconductor body. A plurality of transistors is formed in the semiconductor body. Each transistor has a respective control terminal (354) connected to a common control terminal (321) and a respective current path connected between the external terminal and the reference terminal. A capacitor (314) is connected between the semiconductor body and the external terminal. A resistor (318) is connected between the semiconductor body and the reference terminal.
摘要:
The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enter a snapback region and begin to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.