公开(公告)号：US20060138547A1

公开(公告)日：2006-06-29

申请号：US11356256

申请日：2006-02-16

申请人： Robert Steinhoff

发明人： Robert Steinhoff

IPC分类号： H01L23/62

CPC分类号： H01L29/78 ,  H01L27/0266 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to electro static discharge (ESD) protection circuitry. Multiple techniques are presented to adjust one or more ends of one or more fingers of an ESD protection device so that the ends of the fingers have a reduced initial trigger or breakdown voltage as compared to other portions of the fingers, and in particular to central portions of the fingers. In this manner, most, if not all, of the adjusted ends of the fingers are likely to trigger or fire before any of the respective fingers completely enter a snapback region and begin to conduct ESD current. Consequently, the ESD current is more likely to be distributed among all or substantially all of the plurality of fingers rather than be concentrated within one or merely a few fingers. As a result, potential harm to the ESD protection device (e.g., from current crowding) is mitigated and the effectiveness of the device is improved.

摘要翻译： 本发明涉及静电放电（ESD）保护电路。 提出了多种技术来调整ESD保护装置的一个或多个手指的一个或多个端部，使得与手指的其它部分相比，指状物的端部具有减小的初始触发或击穿电压，并且特别是与中心部分 的手指。 以这种方式，大多数（如果不是全部）手指的调整的端部可能在任何相应的手指完全进入快速恢复区域并开始导通ESD电流之前触发或触发。 因此，ESD电流更可能分布在所有或基本上所有多个指状物中，而不是集中在一个或仅几个手指内。 结果，减轻了对ESD保护装置的潜在危害（例如，来自当前拥挤），并且改善了装置的有效性。

公开(公告)号：US20050087761A1

公开(公告)日：2005-04-28

申请号：US10692606

申请日：2003-10-24

申请人： Robert Steinhoff

发明人： Robert Steinhoff

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/00 ,  H01L29/74

CPC分类号： H01L27/0262

摘要： The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

公开(公告)号：US06784496B1

公开(公告)日：2004-08-31

申请号：US09668999

申请日：2000-09-25

申请人： Jonathan Brodsky ,  Robert Steinhoff ,  Thomas A. Vrotsos

发明人： Jonathan Brodsky ,  Robert Steinhoff ,  Thomas A. Vrotsos

IPC分类号： H01L2362

CPC分类号： H01L27/0266

摘要： A CDM clamp circuit integrated into the interface circuit it is protecting on an integrated circuit. Generally, the integrated CDM clamp circuit and interface circuit are adjacent to each other and share a common device element or component, thus eliminating the need for a metal interconnect. Because there is no interconnect, the parasitic resistance and inductance are also minimized or eliminated from the circuit, thus reducing or eliminating excessive voltage drop. Preferably, the CDM clamp circuit is integrated into the circuit that it is protecting by having the two circuits share the same silicon source region. In a preferred embodiment input circuit, the same diffusion region is the source of both the input transistor and its associated CDM clamp transistor.

摘要翻译： 集成在接口电路中的CDM钳位电路，它在集成电路上进行保护。 通常，集成的CDM钳位电路和接口电路彼此相邻并且共享公共器件元件或元件，因此不需要金属互连。 因为没有互连，寄生电阻和电感也被最小化或从电路中消除，从而减少或消除过大的电压降。 优选地，CDM钳位电路通过使两个电路共享相同的硅源区域而被集成到其正在保护的电路中。 在优选实施例的输入电路中，相同的扩散区域是输入晶体管及其相关联的CDM钳位晶体管的源极。

公开(公告)号：US06624481B1

公开(公告)日：2003-09-23

申请号：US10407037

申请日：2003-04-04

申请人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

发明人： Sameer P. Pendharkar ,  Philip L. Hower ,  Robert Steinhoff

IPC分类号： H01L2362

CPC分类号： H01L27/0259 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD robust bipolar transistor (200) that includes first and second bipolar elements (210, 220), wherein a first trigger voltage of the first bipolar element (210) is proximate a second sustaining voltage of the second bipolar element (220). The first and second bipolar elements (210, 220) include first and second bases (214, 224), emitters (216, 226) and collectors (212, 222), respectively. The first and second bases (214, 224) are coupled and the first and second collectors (212, 222) are coupled. The ESD robust bipolar transistor (200) also includes an emitter resistor (250) and a base resistor (260), wherein the emitter resistor (250) couples the first and second emitters (216, 226) and the base resistor (260) couples the second emitter (226) and the first and second bases (214, 224).

摘要翻译： 包括第一和第二双极元件（210,220）的ESD坚固的双极晶体管（200），其中第一双极元件（210）的第一触发电压接近第二双极元件（220）的第二维持电压。 第一和第二双极元件（210,220）分别包括第一和第二基极（214,224），发射极（216,226）和集电极（212,222）。 耦合第一和第二基极（214,224），并且耦合第一和第二集电极（212,222）。 ESD稳健双极晶体管（200）还包括发射极电阻（250）和基极电阻（260），其中发射极电阻（250）将第一和第二发射极（216,226）和基极电阻（260）耦合 第二发射器（226）和第一和第二基极（214,224）。

公开(公告)号：US20070091526A1

公开(公告)日：2007-04-26

申请号：US11257839

申请日：2005-10-25

申请人： Robert Steinhoff ,  David Baldwin ,  Jonathan Brodsky

发明人： Robert Steinhoff ,  David Baldwin ,  Jonathan Brodsky

IPC分类号： H02H9/00

CPC分类号： H02H9/046 ,  H01L27/0255

摘要： An apparatus for reducing current leakage between an input locus and at least one power rail for a system includes, for each respective power rail: (a) A first diode unit coupled between the input locus and a coupling locus. The first diode unit is configured to effect substantially zero potential drop during normal operation of the apparatus. (b) A second diode unit coupled between the coupling locus and the respective power rail. The second diode unit is configured to present no forward bias during normal operation of the apparatus. The first and second diode units cooperate to effect current flow between the input locus and the respective power rail during a predetermined operational condition of the apparatus.

摘要翻译： 用于减少用于系统的输入轨迹和至少一个电源轨之间的电流泄漏的装置包括：对于每个相应的电源轨道：（a）耦合在输入轨迹和耦合轨迹之间的第一二极管单元。 第一二极管单元被配置为在设备的正常操作期间实质上为零的电位降。 （b）耦合在耦合轨迹和相应电力轨之间的第二二极管单元。 第二二极管单元被配置为在设备的正常操作期间不呈现正向偏压。 第一和第二二极管单元协作以在设备的预定操作状态期间在输入轨迹和相应的电力轨道之间实现电流流动。

公开(公告)号：US06940131B2

公开(公告)日：2005-09-06

申请号：US10609920

申请日：2003-06-30

申请人： David John Baldwin ,  Joseph A. Devore ,  Robert Steinhoff ,  Jonathan Brodsky

发明人： David John Baldwin ,  Joseph A. Devore ,  Robert Steinhoff ,  Jonathan Brodsky

IPC分类号： H01L27/02 ,  H01L29/06 ,  H01L29/423 ,  H01L23/62

CPC分类号： H01L29/0692 ,  H01L27/0266 ,  H01L29/4238

摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).

摘要翻译： 本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。 环形N型源极区域（106）通常围绕漏极区域（104）。 源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。 环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。 环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。

公开(公告)号：US06919603B2

公开(公告)日：2005-07-19

申请号：US10426448

申请日：2003-04-30

申请人： Jonathan Brodsky ,  Robert Steinhoff ,  Sameer P. Pendharkar

发明人： Jonathan Brodsky ,  Robert Steinhoff ,  Sameer P. Pendharkar

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H03K19/003 ,  H01L23/62

CPC分类号： H01L27/0248 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) protection structure for protecting against ESD events between signal terminals is disclosed. ESD protection is provided in a first polarity, by a bipolar transistor (4C) formed in an n-well (64; 164), having a collector contact (72; 172) to one signal terminal (PIN1) and its emitter region (68; 168) and base (66; 166) connected to a second signal terminal (PIN2). For reverse polarity ESD protection, a diode (25) is formed in the same n-well (64; 164) by a p+ region (78; 178) connected to the second signal terminal (PIN2), serving as the anode. The cathode can correspond to the n-well (64; 164) itself, as contacted by the collector contact (72; 172). By using the same n-well (64; 164) for both devices, the integrated circuit chip area required to implement this pin-to-pin protection is much reduced.

摘要翻译： 公开了一种用于防止信号端子之间的ESD事件的静电放电（ESD）保护结构。 通过形成在n阱（64; 164）中的双极晶体管（4C）提供ESD保护，其具有到一个信号端子（PIN 1）的集电极触点（72; 172）及其发射极区域 （68; 168）和连接到第二信号端子（PIN 2）的基座（66; 166）。 对于反极性ESD保护，二极管（25）由连接到用作阳极的第二信号端子（PIN2）的p +区（78; 178）形成在同一个n阱（64; 164）中。 阴极可以与收集器触点（72; 172）接触的n阱（64; 164）本身对应。 通过对两个器件使用相同的n阱（64; 164），实现此引脚到引脚保护所需的集成电路芯片面积大大减少。

公开(公告)号：US20050087808A1

公开(公告)日：2005-04-28

申请号：US10951968

申请日：2004-09-28

申请人： Robert Steinhoff

发明人： Robert Steinhoff

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/00 ,  H01L29/74

CPC分类号： H01L27/0262

摘要： The present invention provides a system for electrostatic discharge protection in a semiconductor device, utilizing a silicon-controlled rectifier (502). The system includes the silicon controlled rectifier, which has a first p-type region (508) coupled to a voltage node (504), a first n-type region (512) having a first side adjoining the first p-type region, a second p-type region (510) having a first side adjoining a second side of the first n-type region, and a second n-type region (514) having a first side adjoining a second side of the second p-type region. A clamping structure (506) is intercoupled between the second n-type region and ground, to prevent the junction between the second p-type region and the second n-type region from retaining a forward bias. A switching structure (518) is intercoupled between the second p-type region and ground to ground the second p-type region during normal operation of the semiconductor device.

摘要翻译： 本发明提供一种利用硅可控整流器（502）的半导体器件中的静电放电保护系统。 该系统包括可控硅整流器，其具有耦合到电压节点（504）的第一p型区域（508），具有邻接第一p型区域的第一侧的第一n型区域（512）， 具有邻接第一n型区域的第二侧的第一侧的第二p型区域（510）和与第二p型区域的第二侧邻接的第一侧面的第二n型区域（514）。 夹持结构（506）在第二n型区域和地之间相互配合，以防止第二p型区域和第二n型区域之间的结合保持正向偏压。 在半导体器件的正常操作期间，开关结构（518）在第二p型区域和地之间相互耦合以对准第二p型区域。

公开(公告)号：US20050083619A1

公开(公告)日：2005-04-21

申请号：US10690011

申请日：2003-10-21

申请人： Robert Steinhoff

发明人： Robert Steinhoff

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0262

摘要： An ESD protection device can include a silicon-controlled rectifier (SCR) and an external pumping circuit. The external pumping circuit can be used to forward bias a junction of the SCR. The external pumping circuit can comprise a transistor that can be coupled to a region of the SCR to pump the region.

摘要翻译： ESD保护器件可以包括硅控整流器（SCR）和外部泵浦电路。 外部泵浦电路可用于将SCR的接点向前偏置。 外部泵浦电路可以包括可以耦合到SCR的区域以泵浦该区域的晶体管。

公开(公告)号：US20050083618A1

公开(公告)日：2005-04-21

申请号：US10690006

申请日：2003-10-21

申请人： Robert Steinhoff ,  Jonathan Brodsky

发明人： Robert Steinhoff ,  Jonathan Brodsky

IPC分类号： H01L27/02 ,  H01L29/732 ,  H02H9/00

CPC分类号： H01L27/0259 ,  H01L29/7322

摘要： An ESD protection device includes two bipolar npn transistors that are coupled in series for use in clamping applications. The emitter of the first bipolar transistor can be coupled to a protected node and the emitter of the second bipolar transistor can be coupled to a grounded node. The first bipolar transistor and the second bipolar transistor can share a common collector.

摘要翻译： ESD保护器件包括串联耦合用于钳位应用的两个双极性npn晶体管。 第一双极晶体管的发射极可以耦合到受保护节点，并且第二双极晶体管的发射极可以耦合到接地节点。 第一双极晶体管和第二双极晶体管可共享公共集电极。