公开(公告)号：US20060229680A1

公开(公告)日：2006-10-12

申请号：US11095305

申请日：2005-03-31

Applicant: Fred Chapman ,  Robert Walker ,  Ronald Stickney

Inventor： Fred Chapman ,  Robert Walker ,  Ronald Stickney

IPC: A61N1/39

CPC classification number: A61N1/3925 ,  A61N1/39 ,  A61N1/3993

Abstract: An apparatus and method is provided for a defibrillator that specifies treatment protocols in terms of number of chest compressions instead of time intervals. The defibrillator includes a connection port that is configured to attach with a plurality of electrodes that are capable of delivery of a defibrillation shock and/or sensing one or more physical parameters. An energy storage device capable of storing a charge is attached to the plurality of electrodes. A controller is coupled to the plurality of electrodes and the energy storage device, the controller is configured to provide CPR chest compression instructions in terms of the numbers of CPR chest compressions.

公开(公告)号：US20060181957A1

公开(公告)日：2006-08-17

申请号：US11128829

申请日：2005-05-13

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G11C8/00

CPC classification number: G11C11/40626 ,  G11C7/1045 ,  G11C7/1072 ,  G11C11/406 ,  G11C2211/4061

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract translation: 不存储在SDRAM模块的DRAM阵列中的数据在同步数据传输中从SDRAM模块读取。 被称为寄存器读命令/操作的数据传输类似于定时和操作中针对存储在DRAM阵列中的数据的读命令/操作。 寄存器读命令通过SDRAM控制信号和存储体地址位的唯一编码进行区分。 在一个实施例中，寄存器读取命令包括与MSR或EMSR命令相同的控制信号状态，其中存储体地址设置为唯一值，例如2'b10。 寄存器读取命令可以仅读取单个数据，或者可以利用地址总线来寻址未存储在DRAM阵列中的多个数据。 寄存器读取操作可以是突发读取，并且突发长度可以以各种方式定义。

公开(公告)号：US20060122918A1

公开(公告)日：2006-06-08

申请号：US11007750

申请日：2004-12-08

Applicant: Benjamin Graboske ,  Robert Walker

Inventor： Benjamin Graboske ,  Robert Walker

IPC: G07F19/00 ,  G07B17/00 ,  G06F17/00 ,  G06F7/00

CPC classification number: G06Q30/0278 ,  G06Q10/10 ,  G06Q40/00 ,  G06Q40/12 ,  G06Q50/16

Abstract: A method and apparatus for real time testing of automated valuation models using various indicators of accuracy. These indicators are then weighted according to their value as indicators of accuracy using individualized weighting factors or an equation. A ranking is then computed based upon the factors and their weights. This method is preformed continuously, so as to achieve real-time or periodically updated automated valuation model accuracy rankings.

Abstract translation: 一种使用各种精度指标实时自动评估模型的方法和装置。 然后将这些指标根据其值作为使用个体化加权因子或方程的精度指标进行加权。 然后根据因素及其权重计算排名。 该方法不断进行，以实现实时或定期更新的自动化估价模型精度排名。

公开(公告)号：US20060120655A1

公开(公告)日：2006-06-08

申请号：US11330235

申请日：2006-01-12

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G02F1/295 ,  G02B6/42 ,  G02B6/26

CPC classification number: G02F1/0123 ,  G02F1/225 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/212 ,  G02F2203/25

Abstract: An optical modulator for producing a modulated optical output having a pre-determined frequency chirp is provided. The optical modulator includes an optical splitting device configured to receive and split an optical input signal to be modulated into two optical signals to pass along two waveguide arms made of electro-optic material and an optical combining device configured to receive and combine the two optical signals into said modulated optical output. At least one electrode pair is associated with each waveguide arm, and is electrically connected in series such as to modulate the phase of said optical signals in antiphase in response to a single electrical signal applied thereto. The modulator further includes a capacitive element connected to the electrode pair of one arm such as to modify the division of the single electrical signal such that the magnitude of the electrical signal across the electrode pair of one arm is different to that across the electrode pair of the other arm, thereby imparting the pre-determined frequency chirp in the modulated optical output.

Abstract translation: 提供了一种用于产生具有预定频率啁啾的调制光输出的光调制器。 光调制器包括光分离装置，其被配置为接收和分离待调制的光输入信号以两个光信号通过由电光材料制成的两个波导臂，以及配置成接收和组合两个光信号 进入所述调制光输出。 至少一个电极对与每个波导臂相关联，并且串联电连接，以响应于施加到其上的单个电信号来反相地调制所述光信号的相位。 调制器还包括连接到一个臂的电极对的电容元件，以便修改单个电信号的划分，使得跨越电极对的一个电极对的电信号的幅度不同于电极对的电极对 从而在调制光输出中赋予预定频率啁啾。

公开(公告)号：US20060101356A1

公开(公告)日：2006-05-11

申请号：US10904225

申请日：2004-10-29

Applicant: Robert Allen ,  Cam Endicott ,  Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker ,  Xin Yuan

Inventor： Robert Allen ,  Cam Endicott ,  Fook-Luen Heng ,  Jason Hibbeler ,  Kevin McCullen ,  Rani Narayan ,  Robert Walker ,  Xin Yuan

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  G06F17/5068

Abstract: A method, system and program product for migrating an integrated circuit (IC) design from a source technology without radical design restrictions (RDR) to a target technology with RDR, are disclosed. The invention implements a minimum layout perturbation approach that addresses the RDR requirements. The invention also solves the problem of inserting dummy shapes where required, and extending the lengths of the critical shapes and/or the dummy shapes to meet ‘edge coverage’ requirements.

Abstract translation: 公开了一种用于将集成电路（IC）设计从没有激进设计限制（RDR）的源技术迁移到具有RDR的目标技术的方法，系统和程序产品。 本发明实现了解决RDR要求的最小布局扰动方法。 本发明还解决了在需要时插入虚拟形状的问题，并且延伸临界形状和/或虚拟形状的长度以满足“边缘覆盖”要求。

公开(公告)号：US20050268301A1

公开(公告)日：2005-12-01

申请号：US10854982

申请日：2004-05-26

Applicant: Brian Kelley ,  Robert Walker ,  Marc Nijdam

Inventor： Brian Kelley ,  Robert Walker ,  Marc Nijdam

IPC: G06F9/46 ,  G06F9/48

CPC classification number: G06F9/4843

Abstract: A system for saving application state history information, containing an historical snap-shot of dynamic application state information associated with execution of a first application on a computing device. The application state history information is saved for use in a subsequent re-launch of the first application.

Abstract translation: 一种用于保存应用状态历史信息的系统，其包含与计算设备上的第一应用的执行相关联的动态应用状态信息的历史快照。 应用状态历史信息被保存以用于第一应用的后续重新启动。

公开(公告)号：US20050259493A1

公开(公告)日：2005-11-24

申请号：US11056486

申请日：2005-02-10

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G11C11/406 ,  G11C7/00

CPC classification number: G11C11/40618 ,  G11C11/406

Abstract: A memory system for controlling memory refresh is provided. An embodiment of the memory system includes a memory configured to operate in a self-refresh mode and an auto-refresh mode, the memory having a plurality of memory locations, and a memory controller configured to access a first one of the memory locations while a second one of the memory locations is being refreshed in the auto-refresh mode. Another embodiment of the memory system includes a memory that can communicate its self refresh address to the memory controller A further embodiment includes a memory controller that can communicate an auto-refresh address to a memory.

Abstract translation: 提供了一种用于控制存储器刷新的存储器系统。 存储器系统的实施例包括被配置为以自刷新模式和自动刷新模式操作的存储器，存储器具有多个存储器位置，以及存储器控制器，其被配置为访问存储器位置中的第一个，而 第二个存储器位置正在刷新自动刷新模式。 存储器系统的另一实施例包括可将其自刷新地址传送到存储器控制器的存储器。另外的实施例包括可以将自动刷新地址传送到存储器的存储器控​​制器。

公开(公告)号：US20050208445A1

公开(公告)日：2005-09-22

申请号：US10802463

申请日：2004-03-17

Applicant: Robert Walker ,  Ross Embertson

Inventor： Robert Walker ,  Ross Embertson

IPC: F23G5/24 ,  F23G5/42 ,  F23G7/10 ,  F23D11/36 ,  F23L1/00

CPC classification number: F23G5/42 ,  F23G5/245 ,  F23G7/10

Abstract: A method of combusting a fuel in a burn pot includes forming an ash column within the burn pot, and removing a portion of the ash column. The burn pot includes a first sidewall portion, a second sidewall portion, and a translatable plate interposed between the first sidewall portion and the second sidewall portion. The translatable plate is capable of at least two positions. The translatable plate has an opening therein corresponding substantially to a cross sectional area of an inside area of the first sidewall portion or the second sidewall portion.

Abstract translation: 在燃烧锅中燃烧燃料的方法包括在燃烧罐内形成灰柱，并除去灰塔的一部分。 燃烧锅包括第一侧壁部分，第二侧壁部分和插入在第一侧壁部分和第二侧壁部分之间的可平移板。 可平移板能够至少两个位置。 可平移板具有基本上与第一侧壁部分或第二侧壁部分的内部区域的横截面积对应的开口。

公开(公告)号：US20050144372A1

公开(公告)日：2005-06-30

申请号：US10748224

申请日：2003-12-31

Applicant: Robert Walker

Inventor： Robert Walker

IPC: G06F12/00 ,  G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1694 ,  G11C7/1045

Abstract: A memory device controllable with user-defined commands includes a memory array accessible for reading and writing data therein, a command module that receives user-defined commands for controlling access to the memory array, and a mode module that stores command definitions respectively associated with the user-defined commands. Each command definition includes a memory access command, such as a read command or a write command, and at least one memory access parameter, such as the burst length setting and the read or write latency. By sending a program command to the command module, command definitions of the user-defined commands can be programmed into the mode module. Each memory array access commanded by a user-defined command is controlled in accordance with the memory access parameters in the command definition associated with the user-defined command.

Abstract translation: 用用户定义的命令可控的存储器件包括可访问的用于读取和写入数据的存储器阵列，接收用于控制对存储器阵列的访问的用户定义的命令的命令模块，以及模式模块，其存储与 用户定义的命令。 每个命令定义包括存储器访问命令，诸如读取命令或写入命令，以及至少一个存储器访问参数，例如突发长度设置和读取或写入延迟。 通过向命令模块发送程序命令，用户定义的命令的命令定义可以被编程到模块模块中。 根据与用户定义的命令相关联的命令定义中的存储器访问参数来控制由用户定义的命令命令的每个存储器阵列访问。

公开(公告)号：US20050122135A1

公开(公告)日：2005-06-09

申请号：US10730445

申请日：2003-12-08

Applicant: Robert Walker

Inventor： Robert Walker

IPC: H03K19/0185 ,  H03K19/0175

CPC classification number: H03K19/01855

Abstract: A chip to chip interface comprises a driver configured to provide a first signal in response to a change in first data at one edge of a clock signal and a second signal in response to a change in second data at another edge of the clock signal. The chip to chip interface comprises a receiver configured to receive the first signal and the second signal and toggle a first bit in response to the first signal and toggle a second bit in response to the second signal.

Abstract translation: 芯片到芯片接口包括驱动器，其被配置为响应于时钟信号的一个边缘处的第一数据的改变而提供第一信号，并且响应于在时钟信号的另一个边缘处的第二数据的改变来提供第二信号。 芯片到芯片接口包括被配置为接收第一信号和第二信号并且响应于第一信号而触发第一位并且响应于第二信号而触发第二位的接收器。