公开(公告)号：US4360742A

公开(公告)日：1982-11-23

申请号：US175054

申请日：1980-08-04

申请人： Ronald L. Freyman

发明人： Ronald L. Freyman

IPC分类号： H03K23/50 ,  H03K23/66 ,  H03K21/36 ,  H03K21/34 ,  H03K23/22

CPC分类号： H03K23/66 ,  H03K23/50

摘要： An MOS parallel carry synchronous binary counter/clock rate divider circuit has a chain of simultaneously clocked T flip-flop interconnected by an improved enable logic circuit having a plurality of identical carry stages each associated with a different flip-flop except the first and last flip-flop of the chain. Each carry stage has an input terminal connected to the inverted enable input of its associated flip-flop, an output terminal connected to the inverted enable input of the next flip-flop in the chain, a transmission gate transistor having a conduction channel connected in series between the input and output terminals and a gate connected to the normal output of the associated flip-flop, and a depletion mode load transistor having a conduction channel connected between a VDD power supply terminal and the output terminal and a gate connected to the output terminal. The carry stage associated with the first flip-flop comprises an inverter having an input connected to the normal output of the first flip-flop and an output connected to the inverted enable input of the second flip-flop. The clock rate division signal provided by the output of the last flip-flop in the chain can be made programmable by including a programming network in each carry stage. The programming network comprises one or more transistors having conduction channels coupled in series between the output terminal and ground and having gates responsive to control signals for forcing a logic "0" level on the output terminal.

摘要翻译： MOS并行进位同步二进制计数器/时钟分频器电路具有通过改进的使能逻辑电路互连的同步时钟T触发器链，其具有多个相同的进位级，每个与不同的触发器相关联，除了第一和最后一个翻转 链的一角。 每个进位级具有连接到其相关联的触发器的反相使能输入的输入端子，连接到链中的下一个触发器的反相使能输入的输出端子，具有串联连接的导通通道的传输栅极晶体管 在输入和输出端子之间以及连接到相关联的触发器的正常输出的栅极以及连接在VDD电源端子和输出端子之间的导通沟道的耗尽型负载晶体管和连接到输出端子的栅极 。 与第一触发器相关联的进位级包括具有连接到第一触发器的正常输出的输入的反相器和连接到第二触发器的反相使能输入的输出。 由链中最后一个触发器的输出提供的时钟分频信号可以通过在每个进位阶段中包括一个编程网络来进行可编程。 编程网络包括一个或多个晶体管，其具有串联耦合在输出端子和地之间的导通通道，并具有响应控制信号的栅极，用于强制输出端子上的逻辑“0”电平。

公开(公告)号：US4357675A

公开(公告)日：1982-11-02

申请号：US175056

申请日：1980-08-04

申请人： Ronald L. Freyman

发明人： Ronald L. Freyman

IPC分类号： G06F7/50 ,  G06F7/503 ,  G06F7/506

CPC分类号： G06F7/503 ,  G06F2207/3872

摘要： A chain-type ripple-carry generating circuit having a plurality of cascaded stages is provided with a regeneration network in each stage for restoring the logic level of a carry signal propagating through the stage. In one embodiment of the invention the regeneration network is designed to restore a carry-not bit and comprises an MOS transistor having its conduction channel coupled between the input of the stage and a ground terminal, the gate of the transistor being driven by a two-input NOR gate, one input of the NOR gate being connected to receive a precharge clock signal and the other input being connected to the input of the stage. When the precharge clock signal is at a logic "0" level and the input of the stage receives a carry-not bit at a logic "0" level, the NOR gate drives the MOS transistor into conduction causing the input of the stage to be pulled to substantially ground potential.

摘要翻译： 具有多个级联级的链式波纹携带产生电路在每个级中设置有再生网络，用于恢复通过级传播的进位信号的逻辑电平。 在本发明的一个实施例中，再生网络被设计成恢复进位位，并且包括MOS晶体管，其MOS晶体管的导通通道耦合在级的输入端和接地端子之间，晶体管的栅极由二极管驱动， 输入或非门，NOR门的一个输入被连接以接收预充电时钟信号，另一个输入连接到该级的输入端。 当预充电时钟信号处于逻辑“0”电平并且级的输入接收到逻辑“0”电平的进位位时，或非门将MOS晶体管驱动导通，使得该级的输入为 拉到基本接地电位。

公开(公告)号：US07560967B2

公开(公告)日：2009-07-14

申请号：US11870204

申请日：2007-10-10

申请人： Ronald L. Freyman ,  Craig B. Ziemer

发明人： Ronald L. Freyman ,  Craig B. Ziemer

IPC分类号： H03K11/16

CPC分类号： H03C3/225

摘要： Methods and apparatus are provided for improving phase switching and linearity in an analog phase interpolator. A phase interpolator in accordance with the present invention comprises (i) a plurality of tail current sources that are activated for substantially all times when the phase interpolator is operational; (ii) at least two pairs of input transistor devices, wherein one pair of the input transistor devices is associated with a minimum phase of the phase interpolator and another pair of the input transistor devices is associated with a maximum phase of the phase interpolator; and (iii) a plurality of current steering switches that provide currents generated by the plurality of tail current sources to one or more of the at least two pairs of input transistor devices, based on an applied interpolation control signal.

摘要翻译： 提供了用于改善模拟相位内插器中的相位切换和线性度的方法和装置。 根据本发明的相位插值器包括（i）多个尾电流源，其在相位内插器可操作时基本上被激活; （ii）至少两对输入晶体管器件，其中一对输入晶体管器件与相位内插器的最小相位相关联，另一对输入晶体管器件与相位内插器的最大相位相关联; 以及（iii）多个电流转向开关，其基于所施加的内插控制信号，将多个尾电流源产生的电流提供给所述至少两对输入晶体管器件中的一个或多个。

公开(公告)号：US5081377A

公开(公告)日：1992-01-14

申请号：US586127

申请日：1990-09-21

申请人： Ronald L. Freyman

发明人： Ronald L. Freyman

IPC分类号： H03K3/037 ,  H03K3/356

CPC分类号： H03K3/0375 ,  H03K3/356156

摘要： A latch circuit employs a feedback arrangement comprising a transmisson gate circuit that conducts only when the output node is in a mid-voltage state. At the onset of a metastable state, the feedback arrangement forces a receiving node into its previous stable state, thereby forcing the output node into a stable state. This eliminates or reduces the possibility that the latch could remain hung for an indefinite period in a metastable state.

公开(公告)号：US4758974A

公开(公告)日：1988-07-19

申请号：US695907

申请日：1985-01-29

申请人： Evelyn M. Fields ,  Ronald L. Freyman ,  Yehuda Rotblum

发明人： Evelyn M. Fields ,  Ronald L. Freyman ,  Yehuda Rotblum

IPC分类号： G06F7/00 ,  G06F7/485 ,  G06F7/50 ,  G06F7/506 ,  G06F7/508 ,  G06F7/74 ,  G06F7/76 ,  G06F7/38

CPC分类号： G06F7/74 ,  G06F7/485 ,  G06F7/49936

摘要： After performing a floating point addition, it is desired to normalize the sum; that is, shift the most significant digit of the mantissa into the left-most digit location, and adjust the exponent accordingly. Prior art techniques required performing the addition before calculating the number of shifts required. The present technique determines an approximate shift from the addends during addition, resulting in a significant time saving.

摘要翻译： 在执行浮点添加之后，期望归一化总和; 也就是将尾数的最高有效位移动到最左边的数字位置，并相应地调整指数。 现有技术需要在计算所需的班次数之前执行加法。 本技术确定了在添加期间从加数的近似偏移，导致显着的时间节省。

公开(公告)号：US4546276A

公开(公告)日：1985-10-08

申请号：US402922

申请日：1982-07-29

申请人： Ronald L. Freyman ,  Yehuda Rotblum

发明人： Ronald L. Freyman ,  Yehuda Rotblum

IPC分类号： H03K19/017 ,  H03K4/24 ,  H03K17/06 ,  H03K17/687 ,  H03K19/094

CPC分类号： H03K19/01714

摘要： An MOS driver circuit which provides full VDD and VSS output logic levels uses a bootstrap capacitor and a delay circuit whose delay is controlled by potential of the terminal which is bootstrapped. Adverse effects of processing variations are limited because the delay time of the delay circuit is determined by the components which selectively control the potential of the bootstrapped terminal.

摘要翻译： 提供完整的VDD和VSS输出逻辑电平的MOS驱动器电路使用自举电容器和延迟电路，延迟电路的延时由被引导的端子的电位控制。 由于延迟电路的延迟时间由有选择地控制自举终端的电位的组件确定，所以处理变化的不利影响是有限的。