摘要:
A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.
摘要:
A method of allocating a resource in a computer system having a plurality of operating systems, and related system, are disclosed. In at least one embodiment, the method includes providing an advanced configuration and power interface (ACPI) operating to facilitate interactions between at least one of the plurality of the operating systems and one or more of the resource, a hardware device, and firmware, and determining whether the resource is allocated to a first of the plurality of operating systems. The method further includes ejecting the resource from the first operating system, and allocating the resource to a second of the plurality of operating systems.
摘要:
Embodiments of the present invention are directed to enhancing VPAR monitors to allow an active VPAR to be moved from one machine to another, as well as to enhancing virtual-machine monitors to move active VPARs from one machine to another. Because traditional VPAR monitors lack access to many computational resources and to executing-operating-system state, VPAR movement is carried out primarily by specialized routines executing within active VPARs, unlike the movement of guest operating systems between machines carried out by virtual-machine-monitor routines.
摘要:
Implementations of speedy boot for computer systems are disclosed. In an exemplary embodiment, a method of speedy boot for a computer system may include invoking a platform management interrupt (PMI) to soft reset a processor without resetting hardware for the processor. The method may also include bypassing at least some initialization procedures and tests to speed recovery of the computer system to a usable state. The method may also include resetting operating system interfaces and loading the operating system.
摘要:
A system and method updating firmware of cells in cellular, high availability, computing systems. One or more cells having missing, obsolete, corrupt, or otherwise errored firmware when compared to other cells in the partition are identified as mismatched cells. An update cell having desired firmware transmits an update message to each mismatched cell via a manageability system slow speed interconnect. In response to the update message, each mismatched cell enables a high speed interconnect over which they can receive the desired firmware. The update cell transmits the update firmware to each mismatched cell via the high speed interconnect.
摘要:
An apparatus and method for distributing interrupts to Intel® Architecture (IA)-32 processors includes a system bus having a number of nodes. Each node includes a bridge that couples the system bus to a processor bus. The processor bus may include multiple IA-32 processors. The system bus may include any number of nodes. Interrupt transactions appearing on the system bus are converted by the bridge to interrupt signals. The bridge asserts the interrupt signals at one of two pins on a target IA-32 processor. One pin may be programmed to receive non-maskable interrupts and the other pin may be programmed to receive external interrupts. The bridge incorporates a priority and threshold mechanism. The bridge includes a buffer to store pending interrupt signals. The apparatus and method may be used in a mixed IA-32 and IA-64 computer architecture that uses IA-64 components to receive interrupts and uses the bridge to convert the transactions on an IA-64 bus into interrupt signal assertions to an IA-32 processor.
摘要:
A method of allocating a resource in a computer system having a plurality of operating systems, and related system, are disclosed. In at least one embodiment, the method includes providing an advanced configuration and power interface (ACPI) operating to facilitate interactions between at least one of the plurality of the operating systems and one or more of the resource, a hardware device, and firmware, and determining whether the resource is allocated to a first of the plurality of operating systems. The method further includes ejecting the resource from the first operating system, and allocating the resource to a second of the plurality of operating systems.
摘要:
A system comprises at least one processor, and supporting firmware for supporting at least one function of the at least one processor. The system further comprises logic operable to expand the functionality of the at least one function in a fashion that is not natively supported by the supporting firmware, and an interposer for supporting the expanded functionality of the at least one function. A method for expanding the functionality of an execution unit of a system comprises implementing an execution unit in a system, and implementing pre-existing support firmware for the execution unit in the system, wherein the pre-existing support firmware supports at least one function of the execution unit. The method further comprises implementing logic expanding the at least one function in a manner not supported by the pre-existing support firmware, and implementing an interposer to support the expansion of the at least one function.
摘要:
An apparatus and a method are provided to distribute interrupts from a system bus to Intel® Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.
摘要:
A solid-state storage system is described with a method for adjusting the frequency of data retention operations. The data retention operation frequency can be increased or decreased according to a variety of environmental factors such as error code frequency, system temperature, altitude, and other operating conditions. These factors can indicate an increased or decreased risk of failure and accordingly provide increased or decreased rates of data retention operations.