公开(公告)号：US20050060531A1

公开(公告)日：2005-03-17

申请号：US10662563

申请日：2003-09-15

申请人： Michael Davis ,  Russ Herrell ,  David Maciorowski ,  Paul Mantey ,  Michael Young ,  Danial Zilavy

发明人： Michael Davis ,  Russ Herrell ,  David Maciorowski ,  Paul Mantey ,  Michael Young ,  Danial Zilavy

IPC分类号： G06F9/445

CPC分类号： G06F15/177 ,  G06F9/4405

摘要： A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

摘要翻译： 在蜂窝计算机系统的每个小区上提供机器可读标识寄存器。 在系统启动期间读取识别寄存器以识别处理器类型，其可以包括与该单元相关联的指令集体系结构（ISA）。 处理器类型信息用于确保向单元的处理器提供兼容的引导映像。 在另一个实施例中，系统管理子系统具有版本选择标志。 当版本选择标志处于第一状态时，提供给单元的处理器的兼容引导映像是当前引导映像; 其中选择标志处于第二状态，提供给单元的处理器的兼容引导映像是引导映像的旧版本。

公开(公告)号：US20070079152A1

公开(公告)日：2007-04-05

申请号：US11242686

申请日：2005-10-03

申请人： Bradley Winick ,  Shaun Harris ,  Russ Herrell

发明人： Bradley Winick ,  Shaun Harris ,  Russ Herrell

IPC分类号： G06F1/00

CPC分类号： G11C5/14 ,  G11C5/04

摘要： A power throttling method and system for a memory controller in a computer system comprising a power supply module including a plurality of bulk power supplies (“BPSs”) are described. In one embodiment, each of the at BPSs provides to a power output monitor a status signal indicative of a status thereof. Responsive to receipt of the status signals, the power output monitor determines whether a bulk power supply capacity is below system power requirements. Responsive to a positive determination, the power output monitor drives a throttle control signal to the memory controller to a level indicative of an over-threshold state.

摘要翻译： 描述了包括包括多个大容量电源（“BPS”）的电源模块的计算机系统中的存储器控​​制器的功率节流方法和系统。 在一个实施例中，每个BPS向功率输出监视器提供指示其状态的状态信号。 响应于接收状态信号，电源输出监视器确定大容量电源容量是否低于系统电源要求。 响应于肯定确定，功率输出监视器将存储器控制器的油门控制信号驱动到指示过阈值状态的水平。

公开(公告)号：US20070016724A1

公开(公告)日：2007-01-18

申请号：US11166608

申请日：2005-06-24

申请人： Blaine Gaither ,  Russ Herrell ,  Judson Veazey

发明人： Blaine Gaither ,  Russ Herrell ,  Judson Veazey

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/023 ,  G06F2212/401

摘要： Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

摘要翻译： 描述了通过选择性地控制用于将数据传送到存储器和/或从存储器传送数据的突发模式协议来（de）压缩数据的系统，方法，媒体和其他实施例，其中有助于增加存储器传送带宽的时间和位置。 。 一个示例性系统实施例包括存储器控制器，其被配置为（de）压缩存储器，以操纵与压缩数据相关联的大小数据，以及选择性地操纵将压缩数据传送到和/或从随机存取存储器传送的突发模式协议。

公开(公告)号：US20060161419A1

公开(公告)日：2006-07-20

申请号：US11039621

申请日：2005-01-20

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F9/455

CPC分类号： G06F13/105

摘要： Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

摘要翻译： 描述了与外部虚拟化相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括位于集成电路外部的仿真逻辑，其可以可操作地连接到该集成电路。 示例仿真逻辑可以包括被配置为虚拟化由集成电路执行的功能的一部分的虚拟化逻辑。 该部分可以通过与该部分相关联的地址来识别。 示例仿真逻辑还可以包括可操作地连接到虚拟化逻辑并且被配置为存储与虚拟化功能的部分相关联的状态数据的数据存储。

公开(公告)号：US20060143357A1

公开(公告)日：2006-06-29

申请号：US11024575

申请日：2004-12-29

申请人： Mark Shaw ,  Russ Herrell ,  Stuart Berke

发明人： Mark Shaw ,  Russ Herrell ,  Stuart Berke

IPC分类号： G06F13/00

CPC分类号： G06F15/17375 ,  G06F15/8007

摘要： In an embodiment, a multi-processor computer system includes multiple cells, where a cell may include one or more processors and memory resources. The system may further include a global crossbar network and multiple cell-to-global-crossbar connectors, to connect the multiple cells with the global crossbar network. In an embodiment, the system further includes at least one cell-to-cell connector, to directly connect at least one pair of the multiple cells. In another embodiment, the system further includes one or more local crossbar networks, multiple cell-to-local-crossbar connectors, and local input/output backplanes connected to the one or more local crossbar networks.

摘要翻译： 在一个实施例中，多处理器计算机系统包括多个小区，其中小区可以包括一个或多个处理器和存储器资源。 该系统还可以包括全局交叉网络和多个小区到全局交叉连接器，以将多个小区与全局交叉网络连接。 在一个实施例中，系统还包括至少一个单元到单元连接器，以直接连接至少一对多个单元。 在另一个实施例中，该系统还包括一个或多个本地交叉网络，多个小区到本地交叉连接器以及连接到一个或多个本地交叉网络的本地输入/输出背板。

公开(公告)号：US08473673B2

公开(公告)日：2013-06-25

申请号：US11166608

申请日：2005-06-24

申请人： Blaine Douglas Gaither ,  Russ Herrell ,  Judson Eugene Veazey

发明人： Blaine Douglas Gaither ,  Russ Herrell ,  Judson Eugene Veazey

IPC分类号： G06F13/00

CPC分类号： G06F12/023 ,  G06F2212/401

摘要： Systems, methodologies, media, and other embodiments associated with (de)compressing data at a time and in a location that facilitates increasing memory transfer bandwidth by selectively controlling a burst-mode protocol used to transfer data to and/or from a memory are described. One exemplary system embodiment includes a memory controller configured to (de)compress memory, to manipulate size data associated with compressed data, and to selectively manipulate a burst-mode protocol employed in transferring compressed data to and/or from random access memory.

摘要翻译： 描述了通过选择性地控制用于将数据传送到存储器和/或从存储器传送数据的突发模式协议来（de）压缩数据的系统，方法，媒体和其他实施例，其中有助于增加存储器传送带宽的时间和位置。 。 一个示例性系统实施例包括存储器控制器，其被配置为（de）压缩存储器，以操纵与压缩数据相关联的大小数据，以及选择性地操纵将压缩数据传送到和/或从随机存取存储器传送的突发模式协议。

公开(公告)号：US20060123172A1

公开(公告)日：2006-06-08

申请号：US11006964

申请日：2004-12-08

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.