公开(公告)号：US20060129743A1

公开(公告)日：2006-06-15

申请号：US11000279

申请日：2004-11-30

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F12/14

CPC分类号： G06F9/45537

摘要： Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

公开(公告)号：US20060020769A1

公开(公告)日：2006-01-26

申请号：US10898590

申请日：2004-07-23

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F15/00

CPC分类号： G06F9/5077

摘要： Techniques are provided for allocating a plurality of resources on a chip to a plurality of partitions in a partitionable computer system. In one embodiment, a resource allocated to a first partition generates a physical address in an address space allocated to the first partition. A partition identification value identifies the first partition. The first partition identification value is stored in the first physical address to produce a partition-identifying address, which may be transmitted to a system fabric. In another embodiment, a transaction is received which includes a source terminus identifier identifying a source device which transmitted the transaction. It is determined, based on the source terminus identifier, whether the source device is allocated to the same partition as any of the plurality of resources. If the source device is so allocated, the transaction is transmitted to a resource that is allocated to the same partition as the source device.

公开(公告)号：US20060123172A1

公开(公告)日：2006-06-08

申请号：US11006964

申请日：2004-12-08

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

公开(公告)号：US20060161419A1

公开(公告)日：2006-07-20

申请号：US11039621

申请日：2005-01-20

申请人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

发明人： Russ Herrell ,  Gerald Kaufman ,  John Morrison

IPC分类号： G06F9/455

CPC分类号： G06F13/105

摘要： Systems, methodologies, media, and other embodiments associated with external virtualization are described. One exemplary system embodiment includes an emulation logic located external to an integrated circuit to which it may be operably connected. The example emulation logic may include a virtualization logic that is configured to virtualize a portion of a function performed by the integrated circuit. The portion may be identifiable by an address associated with the portion. The example emulation logic may also include a data store that is operably connected to the virtualization logic and that is configured to store a state data associated with virtualizing the portion of the function.

摘要翻译： 描述了与外部虚拟化相关联的系统，方法，媒体和其他实施例。 一个示例性系统实施例包括位于集成电路外部的仿真逻辑，其可以可操作地连接到该集成电路。 示例仿真逻辑可以包括被配置为虚拟化由集成电路执行的功能的一部分的虚拟化逻辑。 该部分可以通过与该部分相关联的地址来识别。 示例仿真逻辑还可以包括可操作地连接到虚拟化逻辑并且被配置为存储与虚拟化功能的部分相关联的状态数据的数据存储。

公开(公告)号：US5416893A

公开(公告)日：1995-05-16

申请号：US143686

申请日：1993-10-26

申请人： Russ Herrell ,  Joe Baldwin ,  Christopher G. Wilcox

发明人： Russ Herrell ,  Joe Baldwin ,  Christopher G. Wilcox

IPC分类号： G06T11/20 ,  G06T15/40 ,  G06T15/10

CPC分类号： G06T15/405

摘要： A system for implementing polygon edging of objects in a graphics display. In a first pass, the system renders the polygon fill with z-buffer comparison and replace enabled, however, for each pixel written to the display frame buffer and z-buffer, an edging plane bit for the pixel is set. A second pass renders the polygon edges with z-buffer comparison and z-buffer replace enabled and uses the edging plane bit as a virgin bit. A third pass re-renders the polygon fill, but only resets the edging plane bit for each pixel. The system may also use a virgin bit available in the z-buffer as the edging plane bit.

摘要翻译： 用于在图形显示器中实现对象的多边形边缘的系统。 在第一次通过中，系统通过z缓冲区比较并使能多边形填充，然而，对于写入显示帧缓冲区和z缓冲区的每个像素，设置像素的边缘平面位。 第二遍通过z-缓冲区比较和Z缓冲区替换启用多边形边缘，并使用边缘平面位作为处女位。 第三遍重新渲染多边形填充，但仅复位每个像素的边缘平面位。 该系统还可以使用z缓冲器中可用的处女位作为边缘平面位。

公开(公告)号：US20050177688A1

公开(公告)日：2005-08-11

申请号：US11049306

申请日：2005-02-01

申请人： Blain Gaither ,  Russ Herrell

发明人： Blain Gaither ,  Russ Herrell

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F15/16

CPC分类号： G06F12/0822 ,  G06F12/082

摘要： A computer system maintains a list of tags (called a Global Ownership Tag List (GOTL)) for all the cache lines in the system that are owned by a cache. The GOTL is used for cache coherence. There may be one central GOTL. Alternatively, the GOTL may be distributed, so that every device that can request a copy of memory data maintains a local copy of the GOTL. The GOTL can be limited to a relatively small size. For a limited size list, a tag may need to be evicted to make room for a new tag. A line associated with an evicted tag must be written back to memory.

公开(公告)号：US20050060531A1

公开(公告)日：2005-03-17

申请号：US10662563

申请日：2003-09-15

申请人： Michael Davis ,  Russ Herrell ,  David Maciorowski ,  Paul Mantey ,  Michael Young ,  Danial Zilavy

发明人： Michael Davis ,  Russ Herrell ,  David Maciorowski ,  Paul Mantey ,  Michael Young ,  Danial Zilavy

IPC分类号： G06F9/445

CPC分类号： G06F15/177 ,  G06F9/4405

摘要： A machine-readable identification register is provided on each cell of a cellular computer system. The identification register is read during system startup to identify a processor type, which may include an instruction set architecture (ISA), associated with the cell. The processor type information is used to ensure that a compatible boot image is provided to processors of the cell. In another embodiment, the system management subsystem has a version selection flag. When the version selection flag is in a first state, the compatible boot image provided to processors of the cell is a current boot image; with the selection flag in a second state the compatible boot image provided to processors of the cell is an older edition of the boot image.

摘要翻译： 在蜂窝计算机系统的每个小区上提供机器可读标识寄存器。 在系统启动期间读取识别寄存器以识别处理器类型，其可以包括与该单元相关联的指令集体系结构（ISA）。 处理器类型信息用于确保向单元的处理器提供兼容的引导映像。 在另一个实施例中，系统管理子系统具有版本选择标志。 当版本选择标志处于第一状态时，提供给单元的处理器的兼容引导映像是当前引导映像; 其中选择标志处于第二状态，提供给单元的处理器的兼容引导映像是引导映像的旧版本。

公开(公告)号：US07600082B2

公开(公告)日：2009-10-06

申请号：US11000279

申请日：2004-11-30

申请人： Russ Herrell ,  Gerald J. Kaufman, Jr. ,  John A. Morrison

发明人： Russ Herrell ,  Gerald J. Kaufman, Jr. ,  John A. Morrison

IPC分类号： G06F13/14

CPC分类号： G06F9/45537

摘要： Systems, methodologies, media, and other embodiments associated with externally trapping transactions are described. One exemplary system embodiment includes an external virtualization logic configured to be operably connected to a processor that does not include internal virtualization support. The example system may include a data store for storing a trappable memory address and a transaction that causes the external virtualization logic to produce a trap.

摘要翻译： 描述了与外部捕获事务相关联的系统，方法，介质和其他实施例。 一个示例性系统实施例包括被配置为可操作地连接到不包括内部虚拟化支持的处理器的外部虚拟化逻辑。 示例系统可以包括用于存储可捕获的存储器地址的数据存储和引起外部虚拟化逻辑产生陷阱的事务。

公开(公告)号：US07480755B2

公开(公告)日：2009-01-20

申请号：US11006964

申请日：2004-12-08

申请人： Russ Herrell ,  Gerald J. Kaufman, Jr. ,  John A. Morrison

发明人： Russ Herrell ,  Gerald J. Kaufman, Jr. ,  John A. Morrison

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： Systems, methodologies, media, and other embodiments associated with a system configured with a trap mode register, multiple interrupt vector address registers, and multiple interrupt vector tables are described. One exemplary system embodiment includes a logic for initializing the trap mode register, for initializing interrupt vector address registers, and for initializing interrupt vector tables. When a trap occurs in a computer configured with the exemplary system, the trap mode register may select, based, for example, on the trap type or a trap data, an associated interrupt vector address register to provide an address of an interrupt vector table through which a trap handler can be invoked.

摘要翻译： 描述了与配置有陷阱模式寄存器，多个中断向量地址寄存器和多个中断向量表的系统相关联的系统，方法，介质和其他实施例。 一个示例性系统实施例包括用于初始化陷阱模式寄存器的逻辑，用于初始化中断向量地址寄存器以及用于初始化中断向量表。 当在配置有示例性系统的计算机中发生陷阱时，陷阱模式寄存器可以例如基于陷阱类型或陷阱数据来选择相关联的中断向量地址寄存器，以通过以下方式提供中断向量表的地址 可以调用陷阱处理程序。

公开(公告)号：US20070079152A1

公开(公告)日：2007-04-05

申请号：US11242686

申请日：2005-10-03

申请人： Bradley Winick ,  Shaun Harris ,  Russ Herrell

发明人： Bradley Winick ,  Shaun Harris ,  Russ Herrell

IPC分类号： G06F1/00

CPC分类号： G11C5/14 ,  G11C5/04

摘要： A power throttling method and system for a memory controller in a computer system comprising a power supply module including a plurality of bulk power supplies (“BPSs”) are described. In one embodiment, each of the at BPSs provides to a power output monitor a status signal indicative of a status thereof. Responsive to receipt of the status signals, the power output monitor determines whether a bulk power supply capacity is below system power requirements. Responsive to a positive determination, the power output monitor drives a throttle control signal to the memory controller to a level indicative of an over-threshold state.

摘要翻译： 描述了包括包括多个大容量电源（“BPS”）的电源模块的计算机系统中的存储器控​​制器的功率节流方法和系统。 在一个实施例中，每个BPS向功率输出监视器提供指示其状态的状态信号。 响应于接收状态信号，电源输出监视器确定大容量电源容量是否低于系统电源要求。 响应于肯定确定，功率输出监视器将存储器控制器的油门控制信号驱动到指示过阈值状态的水平。