公开(公告)号：US20140084293A1

公开(公告)日：2014-03-27

申请号：US13798811

申请日：2013-03-13

Applicant: KOOKMIN UNIVERSITY INDUSTRY ACADEMY COOPERATION FOUNDATION ,  SAMSUNG DISPLAY CO., LTD.

Inventor： Byung Du AHN ,  Jung Hwa KIM ,  Ji Hun LIM ,  Je Hun LEE ,  Dae Hwan KIM ,  Hyun Kwang JUNG

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78693 ,  H01L33/387

Abstract: A thin film transistor array panel includes a substrate, a gate electrode on the substrate, a gate insulating layer on the gate electrode, a semiconductor layer on the gate insulating layer, a source electrode and a drain electrode on the semiconductor layer and facing each other, a floating metal layer between the source electrode and the drain electrode, and a passivation layer covering the source electrode, the drain electrode, and the floating metal layer. The floating metal layer is electrically floating.

Abstract translation: 薄膜晶体管阵列面板包括基板，基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体层，半导体层上的源电极和漏电极，并面对彼此 ，源电极和漏电极之间的浮动金属层，以及覆盖源电极，漏电极和浮置金属层的钝化层。 浮动金属层电浮动。

公开(公告)号：US20130320328A1

公开(公告)日：2013-12-05

申请号：US13683468

申请日：2012-11-21

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Je Hun LEE ,  Jun Ho Song ,  Yun Jong Yeo ,  Hwa Dong Jung

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/66742 ,  H01L21/02205 ,  H01L21/2686 ,  H01L21/28247 ,  H01L21/3086 ,  H01L27/1214 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/86

Abstract: The present invention relates to a thin film transistor, a thin film transistor array panel, and a manufacturing method thereof. A thin film transistor according to an exemplary embodiments of the present invention includes: a gate electrode; a gate insulating layer positioned on or under the gate electrode; a channel region overlapping the gate electrode, the gate insulating layer interposed between the channel region and the gate electrode; and a source region and a drain region, facing each other with respect to the channel region, positioned in the same layer as the channel region, and connected to the channel region, wherein the channel region, the source region, and the drain region comprise an oxide semiconductor, and wherein a carrier concentration of the source region and the drain region is larger than a carrier concentration of the channel region.