公开(公告)号：US20230253336A1

公开(公告)日：2023-08-10

申请号：US18126759

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumhee Ma ,  Chulyong Jang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0362 ,  H01L2224/0603 ,  H01L2224/03462 ,  H01L2224/05582 ,  H01L2224/08146 ,  H01L2224/11462 ,  H01L2224/11622 ,  H01L2224/13026 ,  H01L2224/16148 ,  H01L2224/16155 ,  H01L2924/1431 ,  H01L2924/1437

Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

公开(公告)号：US11626370B2

公开(公告)日：2023-04-11

申请号：US17213025

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumhee Ma ,  Chulyong Jang

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

公开(公告)号：US20220384378A1

公开(公告)日：2022-12-01

申请号：US17651355

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulyong Jang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/48

Abstract: A semiconductor package is provided in which a first adhesive film includes a first extension portion extending relative to a side surface of a first semiconductor chip in a second direction, perpendicular to the first direction, the first extension portion has an upper surface including a first recess concave toward a base chip, each of the plurality of second adhesive films includes a second extension portion extending relative to side surfaces of the plurality of second semiconductor chips in the second direction, and the second extension portion has an upper surface including a second recess concave in the first direction and a lower surface including a protrusion in the first recess or the second recess.