公开(公告)号：US20240030104A1

公开(公告)日：2024-01-25

申请号：US18475546

申请日：2023-09-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulyong Jang

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L23/49833 ,  H01L25/0657 ,  H01L25/0655 ,  H01L23/3171 ,  H01L24/16 ,  H01L24/08 ,  H01L23/49816 ,  H01L2224/08059 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1434 ,  H01L2924/1431 ,  H01L2924/3512 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/02125

Abstract: A method of manufacturing a semiconductor package includes: forming through-vias extending from a front side of a semiconductor substrate into the substrate; forming, on the front side of the semiconductor substrate, a circuit structure including a wiring structure electrically connected to the through-vias; removing a portion of the semiconductor substrate so that at least a portion of each of the through-vias protrudes to a rear side of the semiconductor substrate; forming a passivation layer covering the protruding portion of each of the through-vias; forming trenches recessed along a periphery of a corresponding one of the through-vias; removing a portion of the passivation layer so that one end of each of the through-vias is exposed to the upper surface of the passivation layer; and forming backside pads including a dam structure in each of the trenches, the dam structure being spaced apart from the corresponding one of the through-vias.

公开(公告)号：US12224258B2

公开(公告)日：2025-02-11

申请号：US18380404

申请日：2023-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun Kwon ,  Chulyong Jang

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US20220093521A1

公开(公告)日：2022-03-24

申请号：US17213025

申请日：2021-03-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keumhee Ma ,  Chulyong Jang

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

公开(公告)号：US20240038699A1

公开(公告)日：2024-02-01

申请号：US18380404

申请日：2023-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun KWON ,  Chulyong Jang

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L21/76871 ,  H01L23/481 ,  H01L25/0657 ,  H01L24/73 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/05025 ,  H01L2224/0401 ,  H01L2224/023

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US20220102245A1

公开(公告)日：2022-03-31

申请号：US17325745

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulyong Jang

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

Abstract: A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

公开(公告)号：US11824023B2

公开(公告)日：2023-11-21

申请号：US17465964

申请日：2021-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkyun Kwon ,  Chulyong Jang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768 ,  H01L25/00

CPC classification number: H01L24/05 ,  H01L21/76871 ,  H01L23/481 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/0401 ,  H01L2224/05025

Abstract: A semiconductor chip includes a semiconductor substrate having a first surface and a second surface opposite to the first surface. An active layer is disposed in a portion of the semiconductor substrate adjacent to the first surface. A through electrode extends in the semiconductor substrate in a vertical direction. The through electrode has a lower surface connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate. A passivation layer is disposed on the second surface of the semiconductor substrate. A bonding pad is arranged on a portion of the passivation layer and the upper surface of the through electrode. The bonding pad has a cross-section with a “T” shape in the vertical direction. The bonding pad is connected to the through electrode.

公开(公告)号：US11810837B2

公开(公告)日：2023-11-07

申请号：US17325745

申请日：2021-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulyong Jang

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L23/3171 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0214 ,  H01L2224/0215 ,  H01L2224/02125 ,  H01L2224/08059 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16237 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/3512

Abstract: A semiconductor package includes a plurality of semiconductor chips. At least one of the semiconductor chips includes a semiconductor substrate including a semiconductor layer and a passivation layer having a third surface, a backside pad on the third surface, and a through-via penetrating through the semiconductor substrate. The backside pad includes an electrode pad portion, on the third surface, and a dam structure protruding on one side of the electrode pad portion and surrounding a side surface of the through-via. The dam structure is spaced apart from the side surface of the through-via.

公开(公告)号：US20220199511A1

公开(公告)日：2022-06-23

申请号：US17460745

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjung Jang ,  Chulyong Jang

IPC: H01L23/498 ,  H01L23/00

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm.

公开(公告)号：US12021055B2

公开(公告)日：2024-06-25

申请号：US17651355

申请日：2022-02-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulyong Jang

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/29 ,  H01L23/481 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/5385 ,  H01L23/5386 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29005 ,  H01L2224/29011 ,  H01L2224/29019 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83203 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1434 ,  H01L2924/35121

Abstract: A semiconductor package is provided in which a first adhesive film includes a first extension portion extending relative to a side surface of a first semiconductor chip in a second direction, perpendicular to the first direction, the first extension portion has an upper surface including a first recess concave toward a base chip, each of the plurality of second adhesive films includes a second extension portion extending relative to side surfaces of the plurality of second semiconductor chips in the second direction, and the second extension portion has an upper surface including a second recess concave in the first direction and a lower surface including a protrusion in the first recess or the second recess.

公开(公告)号：US11923286B2

公开(公告)日：2024-03-05

申请号：US17460745

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjung Jang ,  Chulyong Jang

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L24/16 ,  H01L2224/16227

Abstract: A package substrate includes an insulating layer having a mounting surface; a wiring pattern extending in the insulating layer; and a chip bonding pad provided on the mounting surface of the insulating layer and connected to the wiring pattern, the chip bonding pad having a tapered shape in which a horizontal cross-sectional area thereof gradually decreases away from the mounting surface of the insulating layer in a vertical direction. A portion of the chip bonding pad closest to the mounting surface of the insulating layer has a horizontal length of about 20 micrometers (μm) to about 30 μm.