中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.015 seconds)

    INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE
    1.
    发明申请
    INTERCONNECTION STRUCTURE OF A SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE INTERCONNECTION STRUCTURE 有权

    公开(公告)号：US20220093521A1

    公开(公告)日：2022-03-24

    申请号：US17213025

    申请日：2021-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keumhee Ma ,  Chulyong Jang

    IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

    Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

    Semiconductor package including a pad pattern
    2.
    发明授权
    Semiconductor package including a pad pattern 有权

    公开(公告)号：US11688667B2

    公开(公告)日：2023-06-27

    申请号：US17473290

    申请日：2021-09-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keumhee Ma

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

    CPC classification number: H01L23/481 ,  H01L24/06 ,  H01L24/17 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/06181 ,  H01L2224/17181 ,  H01L2225/06513

    Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern.

    Interconnection structure of a semiconductor chip and semiconductor package including the interconnection structure
    4.
    发明授权
    Interconnection structure of a semiconductor chip and semiconductor package including the interconnection structure 有权

    公开(公告)号：US11626370B2

    公开(公告)日：2023-04-11

    申请号：US17213025

    申请日：2021-03-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keumhee Ma ,  Chulyong Jang

    IPC: H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

    Abstract: An interconnection structure of a semiconductor chip may include an interconnection via, a lower pad, a conductive bump, and an upper pad. The interconnection via may be arranged in the semiconductor chip. The lower pad may be arranged on a lower end of the interconnection via exposed through a lower surface of the semiconductor chip. The conductive bump may be arranged on the lower pad. The upper pad may be arranged on an upper end of the interconnection via exposed through an upper surface of the semiconductor chip. The upper pad may have a width wider than a width of the interconnection via and narrower than a width of the lower pad. Thus, an electrical short between the conductive bumps may not be generated in the interconnection structure having a thin thickness.

    Semiconductor package including a pad pattern
    5.
    发明授权
    Semiconductor package including a pad pattern 有权

    公开(公告)号：US11145573B2

    公开(公告)日：2021-10-12

    申请号：US16896529

    申请日：2020-06-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keumhee Ma

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065

    Abstract: A semiconductor package may include a first semiconductor chip and a second semiconductor chip. The first semiconductor chip may include a first semiconductor substrate, a through via structure and a pad pattern. The first semiconductor substrate may include a first surface and a second surface opposite to the first surface, and the second surface may include a recess. The through via structure may pass through the first semiconductor substrate from the first surface to a bottom of the recess of the second surface. An upper surface of the through via structure may protrude from the bottom of the recess. The pad pattern may be electrically connected to the upper surface of the through via structure, and the pad pattern may include a first recess having a concave shape thereon. The second semiconductor chip may include a bump pattern bonded on an inside of the first recess of the pad pattern.

    SEMICONDUCTOR PACKAGE
    6.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250118714A1

    公开(公告)日：2025-04-10

    申请号：US18647087

    申请日：2024-04-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keumhee Ma ,  Wansoo Park

    IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip and directly bonded to the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and directly bonded to the second semiconductor chip, and a molding layer on an upper surface of the first semiconductor chip and on a sidewall of the second semiconductor chip and a sidewall of the third semiconductor chip, wherein the third semiconductor chip includes a third semiconductor substrate including an upper surface at a level, which is lower than an upper surface of the molding layer, and a third upper insulation layer on the upper surface of the third semiconductor substrate, the upper surface of the molding layer, and an inner sidewall of the molding layer.

Patent Agency Ranking