公开(公告)号：US20200027992A1

公开(公告)日：2020-01-23

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20250072107A1

公开(公告)日：2025-02-27

申请号：US18944448

申请日：2024-11-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGIL PARK ,  JAE HYUN PARK ,  DAEWON HA ,  KYUMAN HWANG

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a three-dimensional semiconductor device and its fabrication method. The semiconductor device includes a first active region on a substrate and including a plurality of lower channel patterns and a plurality of lower source/drain patterns that are alternately arranged along a first direction, a second active region on the first active region and including a plurality of upper channel patterns and a plurality of upper source/drain patterns that are alternately arranged along the first direction, a first gate electrode on a first lower channel pattern of the lower channel patterns and on a first upper channel pattern of the upper channel patterns, and a second gate electrode on a second lower channel pattern of the lower channel patterns and on a second upper channel pattern of the upper channel patterns. The second gate electrode may include lower and upper gate electrodes with an isolation pattern interposed therebetween.

公开(公告)号：US20240429057A1

公开(公告)日：2024-12-26

申请号：US18823864

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L21/306 ,  H01L21/20 ,  H01L21/3105 ,  H01L21/762 ,  H01L21/84

Abstract: Methods of forming a semiconductor device and semiconductor device formed by the methods are provided. The methods of forming a semiconductor device may include providing a first substrate and a first bonding layer that is provided on the first substrate, forming a sacrificial pattern and an active pattern on a second substrate, forming a second bonding layer on the active pattern, bonding the second bonding layer onto the first bonding layer, removing the second substrate, and removing the sacrificial pattern to expose the active pattern. Forming the sacrificial pattern and the active pattern on the second substrate may include forming a preliminary sacrificial pattern and the active pattern on the second substrate and oxidizing the preliminary sacrificial pattern. The preliminary sacrificial pattern and the active pattern may be sequentially stacked on the second substrate.

公开(公告)号：US20240413158A1

公开(公告)日：2024-12-12

申请号：US18809922

申请日：2024-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20230197858A1

公开(公告)日：2023-06-22

申请号：US18110961

申请日：2023-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78645 ,  H01L29/6675 ,  H01L29/7827 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/78696

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20220173103A1

公开(公告)日：2022-06-02

申请号：US17675163

申请日：2022-02-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L23/522

Abstract: A semiconductor device includes an active pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connected to the first source/drain pattern.

公开(公告)号：US20200373301A1

公开(公告)日：2020-11-26

申请号：US16870135

申请日：2020-05-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DAEWON HA

IPC: H01L27/092 ,  H01L29/08 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L23/522 ,  H01L21/8238

Abstract: A semiconductor device includes an arrive pattern including a channel region. The channel region is disposed between first and second source/drain patterns that are spaced apart from each other in a first direction. The channel region is configured to connect the first and second source/drain patterns to each other. A gate electrode is disposed on a bottom surface of the active pattern and is disposed between the first and second source/drain patterns. An upper interconnection line is disposed on a top surface of the active pattern opposite to the bottom surface of the active pattern and is connoted to the first source/drain pattern.