公开(公告)号：US20240030291A1

公开(公告)日：2024-01-25

申请号：US18125512

申请日：2023-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM

IPC: H01L29/10 ,  H01L27/092 ,  H01L21/74 ,  H01L21/8238

CPC classification number: H01L29/1083 ,  H01L27/0924 ,  H01L21/74 ,  H01L21/823821 ,  H01L21/823814 ,  H01L21/823892

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate provided with an active pattern, a gate electrode that runs across the active pattern and extends in a first direction, source/drain patterns on the active pattern on opposite sides of the gate electrode, a channel pattern formed of a portion of the active pattern between the source/drain patterns, and a buried layer below the source/drain patterns and the channel pattern. The buried layer includes first segments below the source/drain patterns and a second segment below the channel pattern. The first segments have a first level. The second segment has a second level. The first level is lower than the second level.

公开(公告)号：US20210242349A1

公开(公告)日：2021-08-05

申请号：US17240616

申请日：2021-04-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20200027992A1

公开(公告)日：2020-01-23

申请号：US16504960

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SOONMOON JUNG ,  DAEWON HA ,  SUNGMIN KIM ,  HYOJIN KIM ,  KEUN HWI CHO

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes first active patterns on a PMOSFET section of a logic cell region of a substrate, second active patterns on an NMOSFET section of the logic cell region, third active patterns on a memory cell region of the substrate, fourth active patterns between the third active patterns, and a device isolation layer that fills a plurality of first trenches and a plurality of second trenches. Each of the first trenches is interposed between the first active patterns and between the second active patterns. Each of the second trenches is interposed between the fourth active patterns and between the third and fourth active patterns. Each of the third and fourth active patterns includes first and second semiconductor patterns that are vertically spaced apart from each other. Depths of the second trenches are greater than depths of the first trenches.

公开(公告)号：US20230163213A1

公开(公告)日：2023-05-25

申请号：US17843970

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： SANGGIL LEE ,  SEOKHOON KIM ,  SUNGMIN KIM ,  JUNGTAEK KIM ,  PANKWI PARK ,  DONGSUK SHIN ,  NAMKYU CHO ,  RYONG HA ,  YANG XU

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/49 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L29/7848 ,  H01L29/42312 ,  H01L29/49 ,  H01L29/41791 ,  H01L21/02233 ,  H01L21/02532

Abstract: Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.

公开(公告)号：US20210391433A1

公开(公告)日：2021-12-16

申请号：US17313638

申请日：2021-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  JUHUN PARK ,  DEOKHAN BAE ,  MYUNGYOON UM ,  YURI LEE ,  INYEAL LEE ,  YOONYOUNG JUNG ,  SOOYEON HONG

IPC: H01L29/417 ,  H01L27/092

Abstract: A semiconductor device includes a first active (e.g., PMOSFET) region and an adjacent second active (e.g., NMOSFET) region on a substrate, a device isolation layer on the substrate and defining a first active pattern on the first active region and a second active pattern on the second active region, a gate electrode crossing the first and second active patterns, a first source/drain pattern and a second source/drain pattern adjacent to a side of the gate electrode, an interlayer insulating layer on the gate electrode, a first active contact penetrating the interlayer insulating layer to connect the first source/drain pattern and a second active contact penetrating the interlayer insulating layer to connect the second source/drain pattern and a buffer layer provided in an upper region of the interlayer insulating layer and interposed between the first active contact and the second active contact, wherein the buffer layer includes a material having etch selectivity with respect to the interlayer insulating layer.

公开(公告)号：US20210104612A1

公开(公告)日：2021-04-08

申请号：US16874812

申请日：2020-05-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DEOKHAN BAE ,  SUNGMIN KIM ,  JUHUN PARK ,  YOONYOUNG JUNG

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including: a substrate including a first active region; a first active pattern on the first active region; a gate electrode intersecting the first active pattern and extending in a first direction; a first source/drain pattern on the first active pattern, the first source/drain pattern adjacent to the gate electrode; a first interlayer insulating layer covering the gate electrode and the first source/drain pattern; and an active contact penetrating the first interlayer insulating layer to be electrically connected to the first source/drain pattern, wherein the active contact extends in the first direction, wherein a top surface of the active contact includes: a first protrusion; a second protrusion; and a first depression between the first and second protrusions.

公开(公告)号：US20240321688A1

公开(公告)日：2024-09-26

申请号：US18393837

申请日：2023-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： SUNGMIN KIM

IPC: H01L23/48 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device includes a front-side wiring structure connected to a signal line, a back-side wiring structure arranged below the front-side wiring structure and connected to a power line, and an electronic element between the front-side wiring structure and the back-side wiring structure, wherein the electronic element includes a plurality of gate structures, each of the plurality of gate structures includes a gate electrode, a capping film, and a gate spacer, and the capping film includes a first capping film and a second capping film, the first capping film being on a bottom surface of the gate electrode, and the second capping film being on a top surface of the gate electrode.

公开(公告)号：US20180277543A1

公开(公告)日：2018-09-27

申请号：US15804307

申请日：2017-11-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN KIM ,  DONGWON KIM

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes: channel patterns disposed on a substrate; a pair of source/drain patterns disposed at first and second sides of each of the channel patterns; and a gate electrode disposed around the channel patterns, wherein the gate electrode includes a first recessed top surface between adjacent channel patterns, wherein the channel patterns are spaced apart from the substrate, and wherein the gate electrode is disposed between the substrate and the channel patterns.

公开(公告)号：US20160141392A1

公开(公告)日：2016-05-19

申请号：US15003288

申请日：2016-01-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  SUNG-DAE SUK ,  JAEHOO PARK ,  DONGHO CHA ,  DAEWON HA

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。

公开(公告)号：US20140335673A1

公开(公告)日：2014-11-13

申请号：US14262937

申请日：2014-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： SUNGMIN KIM ,  Sung-Dae Suk ,  Jaehoo Park ,  Dongho Cha ,  Daewon Ha

IPC: H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/02233 ,  H01L21/308 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.

Abstract translation: 制造半导体器件的方法包括：图案化衬底以形成有源鳍片，形成与衬底上的有源鳍片交叉的牺牲栅极图案，在牺牲栅极图案上形成层间绝缘层，去除牺牲栅极图案以形成 间隙区域使层间绝缘层中的活性鳍片曝光，并且氧化由间隙区域暴露的活性鳍片的一部分，以在活性鳍片和衬底之间形成绝缘图案。