公开(公告)号：US11670701B2

公开(公告)日：2023-06-06

申请号：US17019767

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/6656 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.

公开(公告)号：US20230129233A1

公开(公告)日：2023-04-27

申请号：US18088550

申请日：2022-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

公开(公告)号：US20230045681A1

公开(公告)日：2023-02-09

申请号：US17967950

申请日：2022-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donghwan Han ,  Seungchan Yun

IPC: H01L29/78 ,  H01L27/092 ,  H01L27/12 ,  H01L21/8238 ,  H01L29/08

Abstract: A semiconductor device includes a substrate including an active region that extends in a first direction; a gate structure that intersects the active region and that extends in a second direction; a source/drain region on the active region on at least one side of the gate structure; a contact plug on the source/drain region on the at least one side of the gate structure; and a contact insulating layer on sidewalls of the contact plug, wherein a lower end of the contact plug is closer to the substrate than a lower end of the source/drain region.

公开(公告)号：US20210193818A1

公开(公告)日：2021-06-24

申请号：US17019767

申请日：2020-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.