公开(公告)号：US12249603B2

公开(公告)日：2025-03-11

申请号：US17570920

申请日：2022-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Inchan Hwang ,  Hyoeun Park ,  Kang-ill Seo

IPC: H01L27/06 ,  H01L25/07 ,  H01L27/07 ,  H01L27/08 ,  H01L49/02

Abstract: Resistor structures of stacked devices and methods of forming the same are provided. The, resistor structures may include a substrate, an upper semiconductor layer that may be spaced apart from the substrate in a vertical direction, a lower semiconductor layer that may be between the substrate and the upper semiconductor layer, and first and second resistor contacts that may be spaced apart from each other in a horizontal direction. At least one of the upper semiconductor layer, the lower semiconductor layer, and a portion of the substrate may contact the first and second resistor contacts.

公开(公告)号：US20240096984A1

公开(公告)日：2024-03-21

申请号：US18160341

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Tae Sun Kim ,  Wonhyuk Hong ,  Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

公开(公告)号：US20230049816A1

公开(公告)日：2023-02-16

申请号：US17504755

申请日：2021-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： SOOYOUNG PARK ,  Seunghyun Song ,  Byounghak Hong ,  Seungchan Yun

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a first channel layer including a first surface, a second channel layer that is spaced apart from the first channel layer in a first direction and includes a second surface, a first gate electrode and a second gate electrode. The first surface and the second surface may be spaced apart from each other in the first direction and may face opposite directions. The first channel layer may be in the first gate electrode, and the first gate electrode may be absent from the first surface of the first channel layer. The second channel layer may be in the second gate electrode, and the second gate electrode may be absent from the second surface of the second channel layer.

公开(公告)号：US11563108B2

公开(公告)日：2023-01-24

申请号：US17011444

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/84

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including: second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

公开(公告)号：US20210159327A1

公开(公告)日：2021-05-27

申请号：US17011444

申请日：2020-09-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L29/78

Abstract: A semiconductor device including: a first structure including: a first semiconductor pattern protruding from a substrate, the first semiconductor pattern being a channel; a first conductive pattern surrounding the first semiconductor pattern, the first conductive pattern being a gate electrode; a first impurity region under the first semiconductor pattern, the first impurity region contacting the first semiconductor pattern, the first impurity region being a source or drain region; and a second impurity region contacting the first semiconductor pattern, the second impurity region being the other of the source or drain region; and a second structure including:
second semiconductor patterns spaced apart from each other, each of the second semiconductor patterns protruding from the substrate; second conductive patterns surrounding the second semiconductor patterns, respectively; and first contact plugs connected to the second conductive patterns, wherein the first structure is a vfet, and the second structure includes a resistor or a capacitor.

公开(公告)号：US20250149340A1

公开(公告)日：2025-05-08

申请号：US18678183

申请日：2024-05-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Kang-Ill Seo

IPC: H01L21/28 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: Transistor devices are provided. A transistor device includes a substrate and a transistor stack on the substrate. The transistor stack includes a lower transistor and an upper transistor that is on top of the lower transistor. Moreover, the transistor device includes a gate-cut on the substrate, adjacent the transistor stack. The gate-cut has a first sloped sidewall and a second sloped sidewall that is opposite the first sloped sidewall. Related methods of forming transistor devices are also provided.

公开(公告)号：US12278285B2

公开(公告)日：2025-04-15

申请号：US18239677

申请日：2023-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/088 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes a plurality of channel layers disposed on an active region of a substrate and spaced apart from each other in a first direction, a first gate structure surrounding the plurality of channel layers, first source/drain regions disposed on the active region on both lateral sides of the first gate structure and contacting the plurality of channel layers and spaced apart from each other in a second direction, an element isolation layer disposed on an upper portion of the first gate structure, a semiconductor layer disposed on the element isolation layer and having a vertical region extending in the first direction and including second source/drain regions spaced apart from each other in the first direction, and a second gate structure disposed to surround a portion of the vertical region. The semiconductor device further includes first to fourth contact plugs.

公开(公告)号：US20250120127A1

公开(公告)日：2025-04-10

申请号：US18626520

申请日：2024-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myung Yang ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/786 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

Abstract: An integrated circuit device includes a p-type field effect transistor that includes a strained channel, the strained channel comprising a silicon channel and silicon germanium cladding layers on opposing surfaces thereof, the silicon germanium cladding layers abutting the silicon channel without being grown therefrom.

公开(公告)号：US20250107172A1

公开(公告)日：2025-03-27

申请号：US18974171

申请日：2024-12-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghak Hong ,  Seungchan Yun ,  Kang-ill Seo

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A multi-stack semiconductor device includes: a substrate; a multi-stack transistor formed on the substrate and including a nanosheet transistor and a fin field-effect transistor (FinFET) above the nanosheet transistor, wherein the nanosheet transistor includes a plurality nanosheet layers surrounded by a lower gate structure except between the nanosheet layers, the FinFET includes at least one fin structure, of which at least top and side surfaces are surrounded by an upper gate structure, and each of the lower and upper gate structures includes: a gate oxide layer formed on the nanosheet layers and the at least one fin structure; and a gate metal pattern formed on the gate oxide layer. At least one of the lower and upper gate structures includes an extra gate (EG) oxide layer formed between the gate oxide layer and the nanosheet layers and/or between the gate oxide layer and the at least one fin structure.

公开(公告)号：US12176417B2

公开(公告)日：2024-12-24

申请号：US18329206

申请日：2023-06-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungchan Yun ,  Donghwan Han

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A semiconductor device including a substrate including first and second regions, a first transistor on the first region and including a first semiconductor pattern protruding from the first region; a first gate structure covering an upper surface and sidewall of the first semiconductor pattern; first source/drain layers on the first semiconductor pattern at opposite sides of the first gate structure, upper surfaces of the first source/drain layers being closer to the substrate than an uppermost surface of the first gate structure; and a second transistor on the second region and including a second semiconductor pattern protruding from the second region; a second gate structure covering a sidewall of the second semiconductor pattern; and a second source/drain layer under the second semiconductor pattern; and a third source/drain layer on the second semiconductor pattern, wherein the upper surface of the first region is lower than the upper surface of the second region.