公开(公告)号：US20230369214A1

公开(公告)日：2023-11-16

申请号：US18195646

申请日：2023-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeonil Lee ,  Seryeun Yang ,  Hyeran Lee

IPC: H01L23/528

CPC classification number: H01L23/5283 ,  H10B51/10 ,  H10B51/30 ,  H10B51/40

Abstract: A semiconductor device is provided. The semiconductor device includes: first lower conductive lines extending in a first direction and disposed at a first height level; first upper conductive lines extending in the first direction and vertically overlapping the first lower conductive lines at a second height level, higher than the first height level; single crystal semiconductor patterns disposed between the first lower conductive lines and the first upper conductive lines at a third height level; intermediate conductive lines extending in a second direction intersecting the first direction and passing between the single crystal semiconductor patterns, between the first height level and the second height level; and data storage layers including portions between the intermediate conductive lines and the single crystal semiconductor patterns.

公开(公告)号：US20250107099A1

公开(公告)日：2025-03-27

申请号：US18657970

申请日：2024-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeran Lee

IPC: H10B51/20 ,  H01L23/522 ,  H01L23/528 ,  H01L29/78 ,  H10B12/00 ,  H10B53/20

Abstract: A semiconductor device includes a first substrate and first and second memory blocks on the first substrate and spaced apart in a first direction, the first memory block includes first bit lines spaced apart in a second direction, first semiconductor patterns in contact with side surfaces of the first bit lines and extending in a direction, and first capacitors electrically connected to ends of the first semiconductor patterns, the second memory block includes second bit lines spaced apart in the second direction, second semiconductor patterns in contact with side surfaces of the second bit lines and extending in the first direction, and second capacitors electrically connected to ends of the second semiconductor patterns. The first capacitors respectively include a first dielectric layer of one of silicon oxide or metal oxide, and the second capacitors respectively include a second dielectric layer of one of ferroelectric or antiferroelectric materials.

公开(公告)号：US11968824B2

公开(公告)日：2024-04-23

申请号：US18137169

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Sungwoo Kim ,  Bongsoo Kim

IPC: H01L27/10 ,  H01L21/768 ,  H10B12/00

CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/0335 ,  H10B12/09 ,  H10B12/315

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US20230413525A1

公开(公告)日：2023-12-21

申请号：US18189391

申请日：2023-03-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeran Lee ,  Kiseok Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/482 ,  H01L28/90 ,  H10B12/50 ,  H10B12/488

Abstract: A semiconductor memory includes a substrate having a plurality of active regions, a plurality of word lines formed in the substrate and disposed in a plurality of word line trenches extending in a first direction, a plurality of cell pad patterns on the plurality of active regions, a plurality of bit line structures formed on the substrate and extending in a second direction perpendicular to the first direction, and a plurality of isolation insulating patterns filling at least a portion of a plurality of isolation trenches extending between the plurality of cell pad patterns in the second direction, wherein each of the plurality of isolation insulating patterns includes an isolation insulating line portion and an isolation insulating spacer portion connected to each other and forming an integral body. The isolation insulating line portion and the isolation insulating spacer portion being disposed in alternating ones of the plurality of isolation trenches and extend in the second direction.

公开(公告)号：US20230255021A1

公开(公告)日：2023-08-10

申请号：US18137169

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H10B12/00 ,  H01L21/768

CPC classification number: H10B12/485 ,  H01L21/76829 ,  H10B12/09 ,  H10B12/315 ,  H10B12/0335

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11678478B2

公开(公告)日：2023-06-13

申请号：US17667697

申请日：2022-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76829 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.

公开(公告)号：US11264392B2

公开(公告)日：2022-03-01

申请号：US16832268

申请日：2020-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjun Kim ,  Seokhyun Kim ,  Jinhyung Park ,  Hoju Song ,  Hyeran Lee ,  Bongsoo Kim ,  Sungwoo Kim

IPC: H01L29/00 ,  H01L27/108

Abstract: A semiconductor device includes a bit line structure, first and second capping patterns, first and second contact plug structures, and a capacitor. The bit line structure extends on a cell region and a dummy region. The first capping pattern is adjacent the bit line structure on the cell region. The second capping pattern is adjacent the bit line structure on the dummy region. The first contact plug structure is adjacent the bit line structure and the first capping pattern on the cell region, and includes a lower contact plug and a first upper contact plug sequentially stacked. The second contact plug structure is adjacent the bit line structure and the second capping pattern on the dummy region, and includes a dummy lower contact plug and a second upper contact plug sequentially stacked. The capacitor contacts an upper surface of the first contact plug structure on the cell region.