公开(公告)号：US11551776B2

公开(公告)日：2023-01-10

申请号：US17392382

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae Kim ,  Myung Kyu Lee ,  Ki Jun Lee ,  Jun Jin Kong ,  Yeong Geol Song ,  Jin-Hoon Jang

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/18 ,  G11C29/14

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.