公开(公告)号：US11128321B2

公开(公告)日：2021-09-21

申请号：US16882627

申请日：2020-05-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Min Shin ,  Beom Kyu Shin ,  Heon Hwa Cheong ,  Jun Jin Kong ,  Hong Rak Son ,  Yeong Geol Song ,  Se Jin Lim

IPC: H03M13/00 ,  H03M13/39 ,  H03M13/11

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

公开(公告)号：US10700714B2

公开(公告)日：2020-06-30

申请号：US16229153

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Min Shin ,  Beom Kyu Shin ,  Heon Hwa Cheong ,  Jun Jin Kong ,  Hong Rak Son ,  Yeong Geol Song ,  Se Jin Lim

IPC: H03M7/40 ,  H03M13/39 ,  H03M13/11

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

公开(公告)号：US20250078947A1

公开(公告)日：2025-03-06

申请号：US18949589

申请日：2024-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Rae Kim ,  Myung Kyu Lee ,  Ki Jun Lee ,  Jun Jin Kong ,  Yeong Geol Song ,  Jin-Hoon Jang

IPC: G11C29/42 ,  G11C29/00 ,  G11C29/14 ,  G11C29/18 ,  G11C29/44

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

公开(公告)号：US12205661B2

公开(公告)日：2025-01-21

申请号：US18093560

申请日：2023-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae Kim ,  Myung Kyu Lee ,  Ki Jun Lee ,  Jun Jin Kong ,  Yeong Geol Song ,  Jin-Hoon Jang

IPC: G11C29/42 ,  G11C29/00 ,  G11C29/14 ,  G11C29/18 ,  G11C29/44

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

公开(公告)号：US11551776B2

公开(公告)日：2023-01-10

申请号：US17392382

申请日：2021-08-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung-Rae Kim ,  Myung Kyu Lee ,  Ki Jun Lee ,  Jun Jin Kong ,  Yeong Geol Song ,  Jin-Hoon Jang

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/18 ,  G11C29/14

Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.

公开(公告)号：US10164663B2

公开(公告)日：2018-12-25

申请号：US15613659

申请日：2017-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong Min Shin ,  Beom Kyu Shin ,  Heon Hwa Cheong ,  Jun Jin Kong ,  Hong Rak Son ,  Yeong Geol Song ,  Se Jin Lim

IPC: H03M7/40 ,  H03M13/39 ,  H03M13/11

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.