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公开(公告)号：US11211102B2
公开(公告)日：2021-12-28
申请号：US17104114
申请日：2020-11-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US12040046B2
公开(公告)日：2024-07-16
申请号：US18447950
申请日：2023-08-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Hoon Jang , Kyungryun Kim , Young Ju Kim , Seung-Jun Lee , Youngbin Lee , Yeonkyu Choi
CPC classification number: G11C8/18 , G11C7/1045 , G11C7/1066 , G11C7/1093
Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.
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公开(公告)号：US10885950B2
公开(公告)日：2021-01-05
申请号：US16363077
申请日：2019-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US12020767B2
公开(公告)日：2024-06-25
申请号：US17539761
申请日：2021-12-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Sik Moon , Kyung-Soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
CPC classification number: G11C7/1048 , G11C7/1084 , G11C7/222
Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US10607660B2
公开(公告)日：2020-03-31
申请号：US15959344
申请日：2018-04-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Young-Hwa Kim , Tae-Young Oh , Jin-Hoon Jang , Seok-Jin Cho
IPC: G11C5/14 , G11C11/4093 , G11C11/4074 , G11C11/4096
Abstract: A memory device having a plurality of voltage regions and a method of operating the same are provided. The memory device includes a memory cell array, a data path region including data processing blocks transmitting read/write data from/to the memory cell array during read/write operations, and a control signal path region including control blocks controlling the data processing blocks during the read/write operations. The data path region selectively receives a first high power voltage or a first low power voltage in accordance with an operating mode of the memory device. The control signal path region receives the first high power voltage regardless of the operating mode.
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Patent Agency Ranking
公开(公告)号：US12176919B2
公开(公告)日：2024-12-24
申请号：US17988140
申请日：2022-11-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Kijun Lee , Myungkyu Lee , Sunghye Cho , Jin-Hoon Jang , Isak Hwang
Abstract: Disclosed is a memory device which includes a memory cell array that stores first data and first parity data, an error correction code (ECC) circuit that performs ECC decoding based on the first data and the first parity data and outputs error-corrected data and a decoding status flag, and an input/output circuit that provides the error-corrected data and the decoding status flag to a memory controller. The ECC circuit includes a syndrome generator that generates a syndrome based on the first data and the first parity data, a syndrome decoding circuit that decodes the syndrome to generate an error vector, a correction logic circuit that generates the error-corrected data based on the error vector and the first data, and a fast decoding status flag (DSF) generator that generates the decoding status flag based on the syndrome, without the error vector.
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公开(公告)号：US11783880B2
公开(公告)日：2023-10-10
申请号：US17496003
申请日：2021-10-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Hoon Jang , Kyungryun Kim , Young Ju Kim , Seung-Jun Lee , Youngbin Lee , Yeonkyu Choi
CPC classification number: G11C8/18 , G11C7/1045 , G11C7/1066 , G11C7/1093
Abstract: Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.
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8.发明申请公开(公告)号：US20190304517A1
公开(公告)日：2019-10-03
申请号：US16363077
申请日：2019-03-25
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dae-Sik Moon , Kyung-soo Ha , Young-Soo Sohn , Ki-Seok Oh , Chang-Kyo Lee , Jin-Hoon Jang , Yeon-Kyu Choi , Seok-Hun Hyun
Abstract: A method of operating memory devices disposed in different ranks of a multi-rank memory device and sharing a signal line includes receiving, in all of the memory devices included in the multi-rank memory device, on-die termination (ODT) state information of the signal line. The method further includes storing, in each of the memory devices of the multi-rank memory device, the ODT state information of the signal line in a mode register. The method further includes generating, in each of the memory devices of the multi-rank memory device, a control signal based on the ODT state information of the signal line stored in the mode register. The method further includes changing, in each of the memory devices of the multi-rank memory device, an ODT setting of the signal line in response to the control signal.
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公开(公告)号：US20250078947A1
公开(公告)日：2025-03-06
申请号：US18949589
申请日：2024-11-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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公开(公告)号：US12205661B2
公开(公告)日：2025-01-21
申请号：US18093560
申请日：2023-01-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Rae Kim , Myung Kyu Lee , Ki Jun Lee , Jun Jin Kong , Yeong Geol Song , Jin-Hoon Jang
Abstract: A memory device includes a memory cell array including memory cells arranged in a plurality of rows; an ECC engine configured to detect an error in first data that is read from the memory cell array in response to a read command and a read address, to output a first error occurrence signal, and to correct the error in the first data; a row fail detector configured to output a fail row address, which indicates a fail row among the plurality of rows; and a flag generator configured to receive the read address, the first error occurrence signal, and the fail row address, and to generate a decoding state flag, which indicates whether an error is detected and whether an error is corrected, and a fail row flag, which indicates that a read row address included in the read address is the fail row address.
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