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    Half-match deduplication
    3.
    发明授权
    Half-match deduplication 有权

    公开(公告)号：US10860233B2

    公开(公告)日：2020-12-08

    申请号：US16382374

    申请日：2019-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Noam Livne ,  Jun Jin Kong

    IPC: G06F3/06 ,  G06F16/22 ,  G06F12/10

    Abstract: A memory system may include a memory device configured to store data received from a host; and a memory controller configured to, receive a received block of the data and a logical address associated with the data from the host, detect at least one halves of the received block as being duplicate halves based on whether a respective one of the at least one halves of the received block match one or more existing halves of stored blocks stored in the memory device, selectively store the at least one halves of the received block in the memory device based on whether the respective one of the at least one halves are duplicate halves such that the duplicate halves of the received block are not stored in the memory device, and store metadata associated with retrieving the received block.

    Nonvolatile memory devices and methods of controlling the same
    4.
    发明授权
    Nonvolatile memory devices and methods of controlling the same 有权

    公开(公告)号：US10606760B2

    公开(公告)日：2020-03-31

    申请号：US15684252

    申请日：2017-08-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Elona Erez ,  Avner Dor ,  Moshe Twitto ,  Jun Jin Kong

    IPC: G06F12/1009 ,  G06F12/02

    Abstract: A memory system includes a nonvolatile memory device having a plurality of physical sectors, a mapping table, and a memory controller including a plurality of hash functions. The memory controller is configured to access the physical sectors using the mapping table and the hash functions. The memory controller is configured to receive a sequence of logical block addresses (LBAs) from a host and logical sector data for each of the LBAs, generate a first virtual address by operating a selected hash function among the hash functions on a first logical block address (LBA) among the sequence, compress the logical sector data to generate compressed data, and store the compressed data in a first physical sector among the physical sectors that is associated with the first virtual address.

    Memory system architecture including semi-network topology with shared output channels
    8.
    发明授权
    Memory system architecture including semi-network topology with shared output channels 有权

    公开(公告)号：US10127165B2

    公开(公告)日：2018-11-13

    申请号：US14801241

    申请日：2015-07-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Amit Berman ,  Uri Beitler ,  Jun Jin Kong

    IPC: G06F13/28 ,  G06F3/06

    Abstract: A memory system includes a first plurality of nonvolatile memory devices of a first channel of the memory system, the first plurality of memory devices each being connected to a first communications bus; a second plurality of nonvolatile memory devices of a second channel of the memory system, the second plurality of memory devices each being connected to a second communications bus, and a first interconnection between a first memory device and a second memory device, the first memory device being a memory device from among the first plurality of nonvolatile memory devices, the second memory device being a memory device from among the second plurality of nonvolatile memory devices.

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