公开(公告)号：US10892267B2

公开(公告)日：2021-01-12

申请号：US15950616

申请日：2018-04-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Hisakazu Otoi ,  Shigehisa Inoue ,  Yuki Fukuda

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11575 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11526

Abstract: A contact via structure vertically extending through an alternating stack of insulating layers and electrically conductive layers is provided in a staircase region having stepped surfaces. The contact via structure is electrically isolated from each electrically conductive layer of the alternating stack except for an electrically conductive layer that directly underlies a horizontal interface of the stepped surfaces. A laterally-protruding portion of the contact via structure contacts an annular top surface of the electrically conductive layer. The electrical isolation can be provided by a ribbed insulating spacer that includes laterally-protruding annular rib regions at levels of the insulating layers, or can be provided by annular insulating spacers located at levels of the electrically conductive layers. The contact via structure can contact a top surface of an underlying metal interconnect structure that overlies a substrate to provide an electrically conductive path.

公开(公告)号：US10586803B2

公开(公告)日：2020-03-10

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10516025B1

公开(公告)日：2019-12-24

申请号：US16009661

申请日：2018-06-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Hisakazu Otoi ,  Akio Nishida

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11556

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a tunneling dielectric layer, a vertical semiconductor channel, and a vertical stack of charge storage structures. Each of the charge storage structures includes an annular silicon nitride portion, a lower silicon nitride portion underlying the upper silicon nitride portion, and a spacer located between the upper silicon nitride portion and the lower silicon nitride portion. The upper and lower silicon nitride portions may be charge storage regions, while the spacer may be a floating gate or a dielectric spacer.

公开(公告)号：US20190326307A1

公开(公告)日：2019-10-24

申请号：US16023866

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10115895B1

公开(公告)日：2018-10-30

申请号：US15715532

申请日：2017-09-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seje Takaki ,  Jongsun Sel ,  Hisakazu Otoi

IPC: H01L29/06 ,  H01L47/00 ,  H01L45/00 ,  H01L27/24 ,  H01L27/105

Abstract: Dielectric wall structures are formed through a stack of a doped semiconductor material layer, a planar insulating spacer layer, and a sacrificial matrix layer. Gate electrode rails are formed through the dielectric wall structures and the sacrificial matrix layer. A two-dimensional array of rectangular openings is formed by removing remaining portions of the sacrificial matrix layer. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of rectangular openings. Gate dielectrics are formed on sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surround gates is formed, which may be employed as access transistors of a three-dimensional memory device.