公开(公告)号：US11487454B2

公开(公告)日：2022-11-01

申请号：US16704729

申请日：2019-12-05

Applicant: SanDisk Technologies LLC

Inventor： Masatoshi Nishikawa ,  Hardwell Chibvongodze

IPC: G11C16/24 ,  G06F3/06 ,  G06F13/16 ,  G11C16/14 ,  G11C16/04

Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.

公开(公告)号：US11081185B2

公开(公告)日：2021-08-03

申请号：US16444410

申请日：2019-06-18

Applicant: SanDisk Technologies LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C16/08 ,  G11C16/14 ,  H01L23/528 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/26 ,  H01L25/18

Abstract: A memory device is disclosed configured to share word line switches (WLSW) between each word line of two adjacent erase blocks. The word lines are driven from both sides of the memory array to reduces resistive-capacitive (RC) loading during pre-charge/ramp-up periods and during discharge/ramp-down periods for various storage operations. The dual-sided driving of signals combines with synergistic erase block size management to lower read latency (tR) for non-volatile memory media.

公开(公告)号：US20210082506A1

公开(公告)日：2021-03-18

申请号：US17102430

申请日：2020-11-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C16/04 ,  H01L27/11524 ,  G11C16/08 ,  G11C16/16 ,  H01L27/11529 ,  G11C16/26 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  G11C16/24

Abstract: Systems and methods for reducing the size of sub-blocks within a physical memory block for a three-dimensional non-volatile memory using buried source lines are described. The physical memory block may be fabricated using dual buried source lines such that sub-blocks within the physical memory block may be individually selected in both a horizontal word line direction and a vertical NAND string direction. The physical memory block may include a plurality of sub-blocks that are individually selectable and that share bit lines and/or source-side select gate lines. The plurality of sub-blocks that are individually selectable may correspond with different portions of the same NAND string in which a first sub-block of the plurality of sub-blocks connects to a drain-side select gate for the NAND string and a second sub-block of the plurality of sub-blocks connects to a source-side select gate for the NAND string.

公开(公告)号：US10720444B2

公开(公告)日：2020-07-21

申请号：US16136652

申请日：2018-09-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Kiyohiko Sakakibara

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

公开(公告)号：US10600800B2

公开(公告)日：2020-03-24

申请号：US16019856

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Shinsuke Yada ,  Yanli Zhang

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L29/10 ,  H01L29/06 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/762 ,  H01L21/28 ,  H01L21/3105 ,  H01L21/306 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word-line-level electrically conductive layers located over a substrate, and a drain-select-level electrically conductive layer located over the alternating stack. Memory stack structures extend through the alternating stack and the drain-select-level electrically conductive layer. Dielectric divider structures including a respective pair of straight sidewalls and drain-select-level isolation structures including a respective pair of sidewalls that include a respective set of concave vertical sidewall segments divide the drain-select-level electrically conductive layer into multiple strips. The drain-select-level electrically conductive layer and the drain-select-level isolation structures are formed by replacement of a drain-select-level sacrificial material layer with a conductive material and by replacement of drain-select-level sacrificial line structures with dielectric material portions.

公开(公告)号：US11222954B2

公开(公告)日：2022-01-11

申请号：US16828129

申请日：2020-03-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Hardwell Chibvongodze ,  Masatoshi Nishikawa

IPC: G11C11/34 ,  H01L29/423 ,  H01L27/11582 ,  H01L29/417 ,  H01L21/28 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of word-line-isolation insulating layers and word-line-level electrically conductive layers located over a substrate, a plurality of drain-select-level electrodes that are laterally spaced apart from each other overlying the alternating stack, memory stack structures containing a respective vertical semiconductor channel laterally surrounded by a respective memory film and vertically extending through the alternating stack and the plurality of drain-select-level electrodes, inter-select-gate electrodes located between a respective neighboring pair of the drain-select-level electrodes, and inter-select-gate dielectrics located between each of the inter-select-gate electrodes and a neighboring one of the drain-select-level electrodes. The inter-select-gate electrodes are not electrically connected to the drain-select-level electrodes.

公开(公告)号：US10930674B2

公开(公告)日：2021-02-23

申请号：US16878865

申请日：2020-05-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Masatoshi Nishikawa ,  Yanli Zhang

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L21/764 ,  H01L27/1157 ,  H01L29/06 ,  H01L21/822 ,  H01L21/8234 ,  H01L21/8239 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11578 ,  H01L27/11575 ,  H01L27/11519 ,  H01L27/11529

Abstract: A three-dimensional memory device includes alternating stacks of electrically conductive strips and spacer strips located over a substrate and laterally spaced apart among one another by memory stack assemblies. The spacer strips may include air gap strips or insulating strips. Each of the memory stack assemblies includes two two-dimensional arrays of lateral protrusion regions. Each of the lateral protrusion regions comprises a respective curved charge storage element. The charge storage elements may be discrete elements located within a respective lateral protrusion region, or may be a portion of a charge storage material layer that extends vertically over multiple electrically conductive strips. Each of the memory stack assemblies may include two rows of vertical semiconductor channels that laterally overlie a respective vertical stack of charge storage elements.

公开(公告)号：US10734080B2

公开(公告)日：2020-08-04

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11526 ,  G11C16/14 ,  G11C16/10

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US20200185039A1

公开(公告)日：2020-06-11

申请号：US16213382

申请日：2018-12-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Hardwell Chibvongodze ,  Masatoshi Nishikawa ,  Naoki Ookuma ,  Takuya Ariki ,  Toru Miwa

IPC: G11C16/24 ,  H01L27/11526 ,  H01L27/11573 ,  H01L27/11548 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/423 ,  G11C16/04 ,  G11C16/26

Abstract: A three-dimensional memory device includes memory stack structures in multiple memory arrays. Bit lines are split into multiple portions traversing different memory arrays. Each sense amplifier is connected to a first portion of a respective bit line via a respective first switching transistor device, and is connected to a second portion of the respective bit line via a respective second switching transistor device. The switching transistor devices connect each sense amplifier to one portion of the bit lines without connecting to another portion of the bit lines, thereby reducing the RC delay. The switching transistor devices may be provided as vertical field effect transistors located at a memory array level, or may be provided in another semiconductor chip.

公开(公告)号：US10559582B2

公开(公告)日：2020-02-11

申请号：US15997194

申请日：2018-06-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masatoshi Nishikawa ,  Shinsuke Yada ,  Masanori Tsutsumi

IPC: H01L27/24 ,  H01L27/11575 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11548 ,  H01L27/11565 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11519

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate, the source-level material layers containing a source contact layer, an alternating stack of insulating layers and electrically conductive layers located over the substrate-level material layers, memory stack structures extending through the alternating stack, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel having a bottom surface that contacts a respective horizontal surface of the source contact layer, and dielectric pillar structures embedded within the substrate-level material layers and located between the memory stack structures.