公开(公告)号：US20190326306A1

公开(公告)日：2019-10-24

申请号：US16023289

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura ,  Zhixin Cui ,  Kiyohiko Sakakibara

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US10347654B1

公开(公告)日：2019-07-09

申请号：US15977212

申请日：2018-05-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Shuji Minagawa ,  Hisakazu Otoi

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11548 ,  H01L27/11575

Abstract: Memory openings and backside openings are formed through an alternating stack of insulating layers and sacrificial material layers over a substrate. Memory opening fill structures are formed in the memory openings, and sacrificial backside opening fill structures are formed in the backside openings. Cavities are formed in volumes of the backside openings by removing the sacrificial backside opening fill structures. Remaining portions of the sacrificial material layers are replaced with material portions including electrically conductive layers. Each electrically conductive layer is formed as a continuous material layer including holes around the backside openings. Each electrically conductive layer is singulated into a plurality of electrically conductive strips by isotropically recessing the electrically conductive layers around each backside opening. Width-modulated cavities including expanded volumes of the backside openings are formed, and are filled with width-modulated insulating wall structures.

公开(公告)号：US11515317B2

公开(公告)日：2022-11-29

申请号：US16893995

申请日：2020-06-05

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Junpei Kanazawa ,  Hisakazu Otoi ,  Hironori Matsuoka ,  Raiden Matsuno

IPC: H01L27/11582 ,  H01L27/11539 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11556

Abstract: A three-dimensional memory device can include at least one alternating stack of insulating layers and electrically conductive layers located over a semiconductor material layer, memory stack structures vertically extending through the at least one alternating stack, and a vertical stack of dielectric plates interlaced with laterally extending portions of the insulating layers of the at least one alternating stack. A conductive via structure can vertically extend through each dielectric plate and the insulating layers, and can contact an underlying metal interconnect structure. Additionally or alternatively, support pillar structures can vertically extend through the vertical stack of dielectric plates and into an opening through the semiconductor material layer, and can contact lower-level dielectric material layers embedding the underlying metal interconnect structure to enhance structural support to the three-dimensional memory device during manufacture.

公开(公告)号：US10985176B2

公开(公告)日：2021-04-20

申请号：US16366330

申请日：2019-03-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Takaaki Iwai ,  Yoshitaka Otsu ,  Hisakazu Otoi

IPC: H01L27/11 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11558 ,  H01L27/11519 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11524

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

公开(公告)号：US10707314B2

公开(公告)日：2020-07-07

申请号：US15720490

申请日：2017-09-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seje Takaki ,  Jongsun Sel ,  Hisakazu Otoi ,  Chao Feng Yeh

IPC: H01L29/788 ,  H01L29/417 ,  H01L27/02 ,  H01L27/11 ,  H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L29/66

Abstract: A stack including doped semiconductor strips, a one-dimensional array of gate electrode strips, and a dielectric matrix layer is formed over a substrate. A two-dimensional array of openings is formed through the dielectric matrix layer and the one-dimensional array of gate electrode strips. A two-dimensional array of tubular gate electrode portions is formed in the two-dimensional array of openings. Each of the tubular gate electrode portions is formed directly on a respective one of the gate electrode strips. Gate dielectrics are formed on inner sidewalls of the tubular gate electrode portions. Vertical semiconductor channels are formed within each of the gate dielectrics by deposition of a semiconductor material. A two-dimensional array of vertical field effect transistors including surrounding gate electrodes is formed.

公开(公告)号：US11996153B2

公开(公告)日：2024-05-28

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Yuki Mizutani ,  Hisakazu Otoi ,  Masaaki Higashitani ,  Hiroyuki Ogawa

IPC: G11C16/08 ,  G11C8/14 ,  G11C16/04 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C8/14 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.

公开(公告)号：US20190326313A1

公开(公告)日：2019-10-24

申请号：US16024048

申请日：2018-06-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Zhixin Cui ,  Kiyohiko Sakakibara ,  Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kenji Sugiura

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L21/28

Abstract: A method of forming a three-dimensional memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate, forming a patterned template structure around memory openings in a drain-select-level above the alternating stack, forming drain-select-level isolation structures in trenches in the patterned template structure, forming memory stack structures in the memory openings extending through the alternating stack, where each of the memory stack structures includes a memory film and a vertical semiconductor channel, replacing the sacrificial material layers with word lines, and separately replacing the patterned template structure with a drain select gate electrode.

公开(公告)号：US20190280003A1

公开(公告)日：2019-09-12

申请号：US16020817

申请日：2018-06-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Hisakazu Otoi ,  Kensuke Yamaguchi ,  James Kai ,  Zhixin Cui ,  Murshed Chowdhury ,  Johann Alsmeier ,  Tong Zhang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11526 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: Multiple tier structures are stacked over a substrate. Each tier structure includes an alternating stack of insulating layers and sacrificial material layers and a retro-stepped dielectric material portion overlying the alternating stack. Multiple types of openings are formed concurrently during formation of each tier structure. Openings concurrently formed through each tier structure can include at least two types of openings that may be selected from through-tier memory openings, through-tier support openings, and through-tier staircase-region openings. Each through-tier opening is filled with a respective through-tier sacrificial opening fill structure. Stacks of through-tier sacrificial opening fill structures can be removed in stages to form various device components, which include memory stack structures, support pillar structures, and staircase-region contact via structures. The sacrificial material layers are replaced with electrically conductive layers, which are laterally electrically isolated from the staircase-region contact via structures by annular insulating spacers.

公开(公告)号：US10354987B1

公开(公告)日：2019-07-16

申请号：US15928340

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L25/18 ,  H01L27/11582 ,  H01L27/11556

Abstract: Sacrificial pillar structures are formed through a first semiconductor substrate on which first semiconductor devices are subsequently formed. After backside thinning of the first semiconductor substrate, the sacrificial pillar structures are replaced with integrated through-substrate via and pad structures to provide a first semiconductor chip. A second semiconductor chip is provided, which includes a second semiconductor substrate, second semiconductor devices, and second bonding pad structures electrically connected to a respective one of the second semiconductor devices. The first bonding pad structures are bonded to a respective one of the second bonding pad structures by surface activated bonding.

公开(公告)号：US10354980B1

公开(公告)日：2019-07-16

申请号：US15928407

申请日：2018-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuteru Mushiga ,  Akio Nishida ,  Kenji Sugiura ,  Hisakazu Otoi ,  Masatoshi Nishikawa

IPC: H01L25/00 ,  H01L25/065 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/00 ,  H01L21/822

Abstract: Multiple semiconductor chips can be bonded through copper-to-copper bonding. The multiple semiconductor chips include a logic chip and multiple memory chips. The logic chip includes a peripheral circuitry for operation of memory devices within the multiple memory chips. The memory chips can include front side bonding pad structures, backside bonding pad structures, and sets of metal interconnect structures providing electrically conductive paths between pairs of a first side bonding pad structure and a backside bonding pad structure. Thus, electrical control signal can vertically propagate between the logic chip and an overlying memory chip through at least one intermediate memory chip located between them. The backside bonding pad structures can be formed as portions of integrated through-substrate via and pad structures that extend through a respective semiconductor substrate.