公开(公告)号：US11869619B2

公开(公告)日：2024-01-09

申请号：US17828708

申请日：2022-05-31

Applicant: SanDisk Technologies LLC

Inventor： Jang Woo Lee ,  Srinivas Rajendra ,  Anil Pai ,  Venkatesh Prasad Ramachandra

IPC: G11C29/00 ,  G11C29/52 ,  G06F1/12

CPC classification number: G11C29/52 ,  G06F1/12

Abstract: Systems and methods are provided that combine a write duty cycle adjuster with write training to reduce detection and duty cycle errors in memory devices. Various embodiments herein perform write duty cycle adjuster operations to adjust a duty cycle of a clock signal that coordinates a data signal with a data operation on the memory device based on an error in the duty cycle, and performs write training operations to detect a skew between the data signal and the clock signal and adjust a sampling transition of the duty cycle of the clock signal to align with a valid data window of the data signal.

公开(公告)号：US11482262B1

公开(公告)日：2022-10-25

申请号：US17348904

申请日：2021-06-16

Applicant: SanDisk Technologies LLC

Inventor： Jang Woo Lee ,  Srinivas Rajendra ,  Anil Pai ,  Venkatesh Ramachandra

IPC: G06F13/16 ,  G11C7/10 ,  G06F13/40

Abstract: Technology is disclosed herein for per pin internal reference voltage generation for data receivers in non-volatile memory systems. A receiving circuit may have an on-die voltage generator that has inputs to receive a separate voltage magnitude select signal for each data receiver on the receiving circuit. The on-die voltage generator provides a separate reference voltage for each data receiver. This allows the reference voltage for each data receiver to be calibrated separately. A separate reference voltage for each data receiver compensates for variations between data paths, and provides for a wider data valid window than if the same reference voltage were used for all data receivers. Generating the different reference voltages on-die can potentially require a large area, as well as consume considerable power and/or current. A voltage divider and multiplexers may provide the different reference voltages, which saves space and is power and current efficient.

公开(公告)号：US20190109585A1

公开(公告)日：2019-04-11

申请号：US15875519

申请日：2018-01-19

Applicant: SanDisk Technologies LLC

Inventor： Tianyu Tang ,  Venkatesh Ramachandra ,  Srinivas Rajendra

IPC: H03K3/017 ,  H03K17/687 ,  H03M1/66

Abstract: A correction system is configured to correct for duty cycle distortion and/or cross-point distortion in a pair of sample signals. A slope adjustment circuit is configured to generate a plurality of pairs of intermediate signals according to a plurality of drive strengths. A measurement circuit is configured to measure for duty cycle distortion and/or cross-point distortion, and the slope adjustment circuit is configured to set the plurality of drive strengths based on the measurement. The setting of the drive strengths may reduce certain rising and falling slopes of certain transitions of the plurality of intermediate signals, which in turn may reduce duty cycle distortion and/or cross-point distortion in the sample signals.