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    Level-Shifter Circuit for Low-Input Voltages
    11.
    发明申请
    Level-Shifter Circuit for Low-Input Voltages 有权
    低电平输入电平移位电路

    公开(公告)号：US20160182051A1

    公开(公告)日：2016-06-23

    申请号：US14574134

    申请日：2014-12-17

    Applicant: SILICON LABORATORIES INC.

    Inventor： Chao Yang ,  Praveen Kallam

    IPC: H03K19/0185

    CPC classification number: H03K19/018514 ,  H03K19/018528

    Abstract: In some embodiments, a method may include receiving an input signal at an input stage of a circuit and amplifying the input signal using an amplifier of the circuit to produce a level-shifted output signal. The method may further include selectively controlling switches of an active load coupled to the input stage based on the level-shifted output signal to turn off current flow between transitions in the input signal.

    Abstract translation: 在一些实施例中，方法可以包括在电路的输入级接收输入信号，并使用电路的放大器放大输入信号以产生电平移位的输出信号。 该方法还可以包括基于电平移位的输出信号选择性地控制耦合到输入级的有源负载的开关，以截止输入信号中的转换之间的电流。

    Multi-stage delay-locked loop phase detector
    12.
    发明授权
    Multi-stage delay-locked loop phase detector 有权
    多级延迟锁相环相位检测器

    公开(公告)号：US09172361B2

    公开(公告)日：2015-10-27

    申请号：US13840675

    申请日：2013-03-15

    Applicant: Silicon Laboratories Inc.

    Inventor： Praveen Kallam ,  Dennis Sinitsky

    IPC: H03D13/00 ,  H03K5/15

    CPC classification number: H03K5/1504

    Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

    Abstract translation: 相位检测器包括包括多个触发器的相位传播器电路。 每个触发器包括时钟输入，其被配置为接收相对于在多个触发器中的其它触发器接收的时钟信号的相位具有不同相位的时钟信号。 相位检测器还包括耦合到多个触发器中的每个触发器的时钟输入的相位控制器。 相位控制器被配置为向多个触发器提供时钟信号的不同相位，使得不同相位相对于彼此成指数地缩放。

    Apparatus for power regulator with multiple inputs and associated methods
    13.
    发明授权
    Apparatus for power regulator with multiple inputs and associated methods 有权

    公开(公告)号：US09964986B2

    公开(公告)日：2018-05-08

    申请号：US14983413

    申请日：2015-12-29

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy T. Rueger ,  Praveen Kallam ,  Nicholas M. Atkinson

    IPC: G05F3/26

    CPC classification number: G05F3/262

    Abstract: An apparatus includes an integrated circuit (IC). The IC includes a regulator to receive a plurality of input voltages and to provide a regulated output voltage to a load. The regulator includes a plurality of voltage regulators that receive the plurality of input voltages and provide the regulated output voltage as an output of the regulator. The IC further includes a controller that controls the regulator by using a voltage regulator in the plurality of voltage regulators to generate the regulated output voltage from the plurality of input voltages.

    Apparatus for Power Regulator with Multiple Inputs and Associated Methods
    14.
    发明申请
    Apparatus for Power Regulator with Multiple Inputs and Associated Methods 有权

    公开(公告)号：US20170185096A1

    公开(公告)日：2017-06-29

    申请号：US14983413

    申请日：2015-12-29

    Applicant: Silicon Laboratories Inc.

    Inventor： Timothy T. Rueger ,  Praveen Kallam ,  Nicholas M. Atkinson

    IPC: G05F3/26

    CPC classification number: G05F3/262

    Abstract: An apparatus includes an integrated circuit (IC). The IC includes a regulator to receive a plurality of input voltages and to provide a regulated output voltage to a load. The regulator includes a plurality of voltage regulators that receive the plurality of input voltages and provide the regulated output voltage as an output of the regulator. The IC further includes a controller that controls the regulator by using a voltage regulator in the plurality of voltage regulators to generate the regulated output voltage from the plurality of input voltages.

    LINEAR REGULATOR HAVING A CLOSED LOOP FREQUENCY RESPONSE BASED ON A DECOUPLING CAPACITANCE
    17.
    发明申请
    LINEAR REGULATOR HAVING A CLOSED LOOP FREQUENCY RESPONSE BASED ON A DECOUPLING CAPACITANCE 有权
    线性稳压器具有基于解耦电容的闭环频率响应

    公开(公告)号：US20160147239A1

    公开(公告)日：2016-05-26

    申请号：US14551923

    申请日：2014-11-24

    Applicant: Silicon Laboratories Inc.

    Inventor： Shouli Yan ,  Axel Thomsen ,  Praveen Kallam

    IPC: G05F1/575

    CPC classification number: G05F1/575 ,  G05F1/56 ,  G05F1/573

    Abstract: A method includes using a pass device of a linear regulator to provide an output signal to an output of the linear regulator in response to a signal that is received at a control terminal of the pass device. The method includes using the linear regulator to regulate the signal received at the control terminal based at least in part on the output signal; and controlling a closed loop frequency response of the linear regulator to cause a direct current (DC) gain of the linear regulator to extend to a frequency near or at frequency of a zero that is associated with a decoupling capacitor that is coupled to the output of the linear regulator.

    Abstract translation: 一种方法包括使用线性调节器的通过装置来响应于在通过装置的控制端子处接收的信号而向线性调节器的输出提供输出信号。 该方法包括使用线性调节器至少部分地基于输出信号来调节在控制终端处接收到的信号; 以及控制所述线性调节器的闭环频率响应，以使所述线性调节器的直流（DC）增益扩展到与耦合到所述线性调节器的输出的去耦电容器相关联的零点附近或频率处的频率 线性调节器。

    Multi-Stage Delay-Locked Loop Phase Detector
    18.
    发明申请
    Multi-Stage Delay-Locked Loop Phase Detector 有权
    多级延迟锁相环检测器

    公开(公告)号：US20140266370A1

    公开(公告)日：2014-09-18

    申请号：US13840675

    申请日：2013-03-15

    Applicant: SILICON LABORATORIES INC.

    Inventor： Praveen Kallam ,  Dennis Sinitsky

    IPC: H03K5/15

    CPC classification number: H03K5/1504

    Abstract: A phase detector includes a phase propagator circuit including a plurality of flip-flops. Each flip-flop includes a clock input configured to receive a clock signal having a different phase relative to phases of the clock signal received by other flip-flops in the plurality of flip-flops. The phase detector further includes a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops. The phase controller is configured to provide the different phases of the clock signal to the plurality of flip-flops such that the different phases are scaled exponentially relative to one another.

    Abstract translation: 相位检测器包括包括多个触发器的相位传播器电路。 每个触发器包括时钟输入，其被配置为接收相对于在多个触发器中的其它触发器接收的时钟信号的相位具有不同相位的时钟信号。 相位检测器还包括耦合到多个触发器中的每个触发器的时钟输入的相位控制器。 相位控制器被配置为向多个触发器提供时钟信号的不同相位，使得不同相位相对于彼此成指数地缩放。

    Digital signal transfer between multiple voltage domains
    20.
    发明授权
    Digital signal transfer between multiple voltage domains 有权

    公开(公告)号：US10355477B2

    公开(公告)日：2019-07-16

    申请号：US14927810

    申请日：2015-10-30

    Applicant: Silicon Laboratories Inc.

    Inventor： Mohamed Elsayed ,  Matthew Powell ,  Nicholas M. Atkinson ,  Praveen Kallam

    IPC: H02J1/10 ,  G06F1/26 ,  H03K19/0185 ,  G06F1/28 ,  G06F1/30 ,  H02J1/00

    Abstract: Circuitry and methods are provided that may be implemented to transfer digital signals between multiple voltage domains while some of these domains may be invalid, e.g., such as to transfer a digital signal from a source voltage domain to a destination voltage domain while the voltage of the source domain is zero or invalid. Possible implementations include, but are not limited to, for power selection and distribution in an integrated circuit chip that has multiple power sources (e.g., such as main power supply and a backup power supply), and in which at startup the chip is agnostic of (or is not aware of) which power supply or power supplies is actually powered and available.

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